JAJSCQ7A December 2016 – June 2018 SN65DSI84-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHA_DSI_DATA_EQ | Reserved | CHA_DSI_CLK_EQ | Reserved | ||||
R/W | R | R/W | R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | CHA_DSI_DATA_EQ | R/W | 00 | This field controls the equalization for the DSI Channel A Data Lanes
00 – No equalization (default) 01 – 1 dB equalization 10 – Reserved 11 – 2 dB equalization |
5-4 | Reserved | R | Reserved | |
3-2 | CHA_DSI_CLK_EQ | R/W | 00 | This field controls the equalization for the DSI Channel A Clock
00 – No equalization (default) 01 – 1 dB equalization 10 – Reserved 11 – 2 dB equalization |
1-0 | Reserved | R | Reserved |