JAJSFO1G September   2012  – June 2018 SN65DSI84

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     標準アプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 EDS Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
      7. 7.4.7 Operating Modes
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video Stop and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
DSI
tGS DSI LP glitch suppression pulse width 300 ps
LVDS
tc Output clock period 6.49 40 ns
tw High-level output clock (CLK) pulse duration 4/7 tc ns
t0 Delay time, CLK↑ to 1st serial bit position tc = 6.49ns;
Input clock jitter < 25ps (REFCLK)		 -0.15 0.15 ns
t1 Delay time, CLK↑ to 2nd serial bit position 1/7 tc – 0.15 1/7 tc + 0.15 ns
t2 Delay time, CLK↑ to 3rd serial bit position 2/7 tc – 0.15 2/7 tc + 0.15 ns
t3 Delay time, CLK↑ to 4th serial bit position 3/7 tc – 0.15 3/7 tc + 0.15 ns
t4 Delay time, CLK↑ to 5th serial bit position 4/7 tc – 0.15 4/7 tc + 0.15 ns
t5 Delay time, CLK↑ to 6th serial bit position 5/7 tc – 0.15 5/7 tc + 0.15 ns
t6 Delay time, CLK↑ to 7th serial bit position 6/7 tc – 0.15 6/7 tc + 0.15 ns
tr Differential output rise-time See Figure 5 180 500 ps
tf Differential output fall-time
EN, ULPS, RESET
ten Enable time from EN or ULPS tc(o) = 12.9 ns 1 ms
tdis Disable time to standby 0.1
treset Reset time 10 ms
REFCLK
FREFCLK REFCLK Freqeuncy. Supported frequencies: 25 MHz-154 MHz 25 154 MHz
tr, tf REFCLK rise and fall time 100 ps 1ns s
tpj REFCLK Peak-to-Peak Phase Jitter 50 ps
Duty REFCLK Duty Cycle 40% 50% 60%
REFCLK or DSI CLK (DACP/N, DBCP/N)
SSC_CLKIN SSC enabled Input CLK center spread depth (2) 0.5% 1% 2%
Modulation Frequency Range 30 60 KHz
(1) All typical values are at VCC = 1.8 V and TA = 25°C
(2) For EMI reduction purpose, SN65DSI84 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK input. The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N and/or B_CLKP/N.
SN65DSI84 DSI_Rec_Voltage_Definitions_LLSEB9.gifFigure 1. DSI Receiver Voltage Definitions
SN65DSI84 fig15_test_load_LLSEB9.gifFigure 2. Test Load and Voltage Definitions for Flatlink Outputs
SN65DSI84 ULPS_timing_LLSEB9.gif
1. See the ULPS section of the data sheet for the ULPS entry and exit sequence.
2. ULPS entry and exit protocol and timing requirements must be met per MIPI® DPHY specification.
Figure 3. ULPS Timing Definition
SN65DSI84 DSI_HS_Mode_Rec_Timing_ Def_llsec2.pngFigure 4. DSI HS Mode Receiver Timing Definitions
SN65DSI84 fig16_flatlink_timing_LLSEB9.gifFigure 5. SN65DSI84 Flatlink Timing Definitions