JAJSFO1G September   2012  – June 2018 SN65DSI84

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     標準アプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 EDS Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
      7. 7.4.7 Operating Modes
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video Stop and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.2 Reverse LVDS Pin Order Option

For ease of PCB routing, the SN65DSI84 supports swapping/reversing the channel or pin order via configuration register programming. The order of the LVDS pin for LVDS Channel A or Channel B can be reversed by setting the address 0x1A bit 5 CHA_REVERSE_LVDS or bit 4 CHB_REVERSE_LVDS. The LVDS Channel A and Channel B can be swapped by setting the 0x1A.6 EVEN_ODD_SWAP bit. See the corresponding register bit definition for details.