JAJSFO1G September 2012 – June 2018 SN65DSI84
PRODUCTION DATA.
The video resolution parameters required by the panel need to be programmed into the SN65DSI84. For this example, the parameters programmed would be the following:
| Horizontal active = 1920 or 0x780
CHA_ACTIVE_LINE_LENGTH_LOW = 0X80 CHA_ACTIVE_LINE_LENGTH_HIGH = 0x07 |
|
| Horizontal pulse Width = 50 or 0x32
CHA_HSYNC_PULSE_WIDTH_LOW = 0x32 CHA_HSYNC_PULSE_WIDTH_HIGH= 0x00 |
|
| Horizontal back porch = Horizontal blanking – (Horizontal sync offset + Horizontal sync pulse width)
Horizontal back porch = 144– (50 + 50) Horizontal back porch = 44 or 0x2C CHA_HORIZONTAL_BACK_PORCH = 0x2C |
|
| Vertical pulse width = 5
CHA_VSYNC_PULSE_WIDTH_LOW = 0x05 CHA_VSYNC_PULSE_WIDTH_HIGH= 0x00 |
The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C and configuring the following TEST PATTERN GENERATION PURPOSE ONLY registers.
| Vertical active = 1200 or 0x4B0
CHA_VERTICAL_DISPLAY_SIZE_LOW = 0xB0 CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0x04 |
|
| Vertical back porch = Vertical blanking – (Vertical sync offset +Vertical sync pulse width)
Vertical back porch = 20 – (1 + 5) Vertical back porch = 14 or 0x0E CHA_VERTICAL_BACK_PORCH = 0x0E |
|
| Horizontal front porch = Horizontal sync offset
Horizontal front porch = 50 or 0x32 CHA_HORIZONTAL_FRONT_PORCH = 0x32 |
|
| Vertical front porch = Vertical sync offset
Vertical front porch =1 CHA_VERTICAL_FRONT_PORCH = 0x01 |
In this example, the clock source for the SN65DSI84 is the DSI clock. When the MIPI D-PHY clock is used as the LVDS clock source, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLink LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12) must be set to the frequency range of the FlatLink LVDS output clock and DSI Channel A input clock respectively for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) should be set to enable the internal PLL.
| LVDS_CLK_RANGE = 010b-62.5 MHz ≤ LVDS_CLK < 87.5 MHz
HS_CLK_SRC = 1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock DSI_CLK_DIVIDER = 0010b – Divide by 6 CHA_DSI_LANES = 00 – Four lanes are enabled CHA_DSI_CLK_RANGE = 0x62 – 490 MHz ≤ frequency < 495 MHz |