JAJSFO1G September   2012  – June 2018 SN65DSI84

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     標準アプリケーション
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 EDS Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
      7. 7.4.7 Operating Modes
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video Stop and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

The video resolution parameters required by the panel need to be programmed into the SN65DSI84. For this example, the parameters programmed would be the following:

Horizontal active = 1920 or 0x780
CHA_ACTIVE_LINE_LENGTH_LOW = 0X80
CHA_ACTIVE_LINE_LENGTH_HIGH = 0x07
Horizontal pulse Width = 50 or 0x32
CHA_HSYNC_PULSE_WIDTH_LOW = 0x32
CHA_HSYNC_PULSE_WIDTH_HIGH= 0x00
Horizontal back porch = Horizontal blanking – (Horizontal sync offset + Horizontal sync pulse width)
Horizontal back porch = 144– (50 + 50)
Horizontal back porch = 44 or 0x2C
CHA_HORIZONTAL_BACK_PORCH = 0x2C
Vertical pulse width = 5
CHA_VSYNC_PULSE_WIDTH_LOW = 0x05
CHA_VSYNC_PULSE_WIDTH_HIGH= 0x00

The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C and configuring the following TEST PATTERN GENERATION PURPOSE ONLY registers.

Vertical active = 1200 or 0x4B0
CHA_VERTICAL_DISPLAY_SIZE_LOW = 0xB0
CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0x04
Vertical back porch = Vertical blanking – (Vertical sync offset +Vertical sync pulse width)
Vertical back porch = 20 – (1 + 5)
Vertical back porch = 14 or 0x0E
CHA_VERTICAL_BACK_PORCH = 0x0E
Horizontal front porch = Horizontal sync offset
Horizontal front porch = 50 or 0x32
CHA_HORIZONTAL_FRONT_PORCH = 0x32
Vertical front porch = Vertical sync offset
Vertical front porch =1
CHA_VERTICAL_FRONT_PORCH = 0x01

In this example, the clock source for the SN65DSI84 is the DSI clock. When the MIPI D-PHY clock is used as the LVDS clock source, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLink LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12) must be set to the frequency range of the FlatLink LVDS output clock and DSI Channel A input clock respectively for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) should be set to enable the internal PLL.

LVDS_CLK_RANGE = 010b-62.5 MHz ≤ LVDS_CLK < 87.5 MHz
HS_CLK_SRC = 1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock
DSI_CLK_DIVIDER = 0010b – Divide by 6
CHA_DSI_LANES = 00 – Four lanes are enabled
CHA_DSI_CLK_RANGE = 0x62 – 490 MHz ≤ frequency < 495 MHz