JAJSFO1G September   2012  – June 2018 SN65DSI84

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     標準アプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 EDS Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
      7. 7.4.7 Operating Modes
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video Stop and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

ZQE Package
64-Pin (Bump) BGA MICROSTAR JUNIOR
Top View
To minimize the power supply noise floor, provide good decoupling near the SN65DSI84 power pins. The use of four ceramic capacitors (2x 0.1 μF and 2x 0.01 μF) provides good performance. At the least, it is recommended to install one 0.1 μF and one 0.01 μF capacitor near the SN65DSI84. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power inputs pins must be minimized. Placing the capacitor underneath the SN65DSI84 on the bottom of the PCB is often a good choice.

Pin Functions

PIN DESCRIPTION
NAME NO. I/O
DA0P H3 LVDS Input (HS)
CMOS Input (LS)
(Failsafe)		 MIPI® D-PHY Channel A Data Lane 0; data rate up to 1 Gbps.
DA0N J3
DA1P H4 MIPI® D-PHY Channel A Data Lane 1; data rate up to 1 Gbps.
DA1N J4
DA2P H6 MIPI® D-PHY Channel A Data Lane 2; data rate up to 1 Gbps.
DA2N J6
DA3P H7 MIPI® D-PHY Channel A Data Lane 3; data rate up to 1 Gbps.
DA3N J7
DACP H5 MIPI® D-PHY Channel A Clock Lane; operates up to 500 MHz.
DACN J5
NC C2, C1, D2, D1, F2, F1, G2, G1, E2, E1 No connects. These pins should not be connected to any signal, power or ground.
A_Y0P C8 LVDS Output FlatLink™ Channel A LVDS Data Output 0.
A_Y0N C9
A_Y1P D8 FlatLink™ Channel A LVDS Data Output 1.
A_Y1N D9
A_Y2P E8 FlatLink™ Channel A LVDS Data Output 2.
A_Y2N E9
A_Y3P G8 FlatLink™ Channel A LVDS Data Output 3. A_Y3P and A_Y3N shall be left NC for 18 bpp panels.
A_Y3N G9
A_CLKP F8 FlatLink™ Channel A LVDS Clock
A_CLKN F9
B_Y0P B3 FlatLink™ Channel B LVDS Data Output 0.
B_Y0N A3
B_Y1P B4 FlatLink™ Channel B LVDS Data Output 1.
B_Y1N A4
B_Y2P B5 FlatLink™ Channel B LVDS Data Output 2.
B_Y2N A5
B_Y3P B7 FlatLink™ Channel B LVDS Data Output 3. B_Y3P and B_Y3N shall be left NC for 18 bpp panels.
B_Y3N A7
B_CLKP B6 FlatLink™ Channel B LVDS Clock.
B_CLKN A6
RSVD1 H8 CMOS Input/Output with pulldown Reserved. This pin should be left unconnected for normal operation.
RSVD2 B2 CMOS Input with pulldown Reserved. This pin should be left unconnected for normal operation.
ADDR A1 CMOS Input/Output Local I2C Interface Target Address Select. See Table 4. In normal operation this pin is an input. When the ADDR pin is programmed high, it should be tied to the same 1.8 V power rails where the SN65DSI84 VCC 1.8 V power rail is connected.
EN B1 CMOS Input with pullup (Failsafe) Chip Enable and Reset. Device is reset (shutdown) when EN is low.
REFCLK H2 CMOS Input (Failsafe) Optional External Reference Clock for LVDS Pixel Clock. If an External Reference Clock is not used, this pin should be pulled to GND with an external resistor. The source of the reference clock should be placed as close as possible with a series resistor near the source to reduce EMI.
SCL H1 Local I2C Interface Clock.
SDA J1 Open Drain Input/Output (Failsafe) Local I2C Interface Bi-directional Data Signal.
IRQ J9 CMOS Output Interrupt Signal.
GND A2, A8, B9, D5, E4, F4, F5, H9 Power Supply Reference Ground.
VCC A9, B8, D6, E5, E6, F6, J2 1.8 V Power Supply.
VCORE J8 1.1 V Output from Voltage Regulator. This pin must have a 1 µF external capacitor to GND.