SN65DSIx6-Q1 MIPI® DSI to eDP™ Bridge

1 Features

• Embedded DisplayPort™ (eDP™) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
• Implements MIPI® D-PHY Version 1.1 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
• Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1.5 Gbps Per Lane
• Supports 18 bpp and 24 bpp DSI Video Packets With RGB666 and RGB888 Formats
• Suitable for 60 fps 4K 4096 × 2304 Resolution at 18 bpp Color, and WUXGA 1920 × 1200 Resolution with 3D Graphics at 60 fps (120 fps Equivalent)
• MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configuration
• Supports Dual-Channel DSI Odd, Even and Left, Right Operating Modes
• 1.2-V Main VCC Power Supply and 1.8-V Supply for Digital I/Os
• Low-Power Features Include Panel Refresh and MIPI Ultralow Power State (ULPS) Support
• DisplayPort Lane Polarity and Assignment Configurable.
• Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz Frequencies Through External Reference Clock (REFCLK)
• ESD Rating ±2 kV (HBM)
• Packaged in 64-Terminal HTQFP (PAP)
• Temperature Range: –40°C to +85°C

2 Applications

• Tablet PCs, Notebook PCs, Netbooks
• Mobile Internet Devices/Automotive Infotainment

3 Description

The SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSI86-Q1 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.

1. For all available packages, see the package option addendum at the end of the datasheet.

4 Revision History

Changes from * Revision (July 2014) to A Revision

• Changed Description for ADDRESS 0x5A BIT(S) 1:0 from 'Reserved' to 'ASSR_CONTROL' with Bit assignments of 00, 01, 10, and 11 in Table 23.Go
• Added Table 33 in Standard CFR Registers Go

5 Description (continued)

Designed with industry compliant interface technology, the is compatible with a wide range of microprocessors, and is designed with a range of power management features, including panel refresh support, and the MIPI defined ultralow power state (ULPS) support.

The SN65DSI86 Q1 is implemented in a 10-mm × 10-mm HTQFP at 0.5-mm pitch package, and operates across a temperature range from –40°C to +85°C.

In the rest of this document, the SN65DSI86-Q1 is referred to as SN65DSIx6 or DSIx6.