SLLSEJ5A July   2014  – December 2015 SN65DSI86-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 Semi-Auto Link Training
          4. 8.4.5.7.4 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 DSI Design Procedure
          3. 9.2.1.2.3 Example Script
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PAP Package
64-Pin HTQFP
Top View
SN65DSI86-Q1 pin_pap64_sllsej5.gif
See Layout Guidelines for additional information.

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
DA0P 19 I MIPI D-PHY Channel A Data Lane 0; data rate up to 1.5 Gbps.
DA0N 20
DA1P 21 I MIPI D-PHY Channel A Data Lane 1; data rate up to 1.5 Gbps.
DA1N 22
DACP 24 I MIPI D-PHY Channel A Clock Lane; operates up to 750MHz. Under proper conditions, this clock can be used instead of REFCLK to feed DP_PLL
DACN 25
DA2P 27 I MIPI D-PHY Channel A Data Lane 2; data rate up to 1.5 Gbps.
DA2N 28
DA3P 29 I MIPI D-PHY Channel A Data Lane 3; data rate up to 1.5 Gbps.
DA3N 30
DB0P 4 I MIPI D-PHY Channel B Data Lane 0; data rate up to 1.5 Gbps.
DB0N 5
DB1P 6 I MIPI D-PHY Channel B Data Lane 1; data rate up to 1.5 Gbps.
DB1N 7
DBCP 8 I MIPI D-PHY Channel B Clock Lane; operates up to 750 MHz.
DBCN 9
DB2P 10 I MIPI D-PHY Channel B Data Lane 2; data rate up to 1.5 Gbps.
DB2N 11
DB3P 12 I MIPI D-PHY Channel B Data Lane 3; data rate up to 1.5 Gbps.
DB3N 13
ML0P 37 O DisplayPort Lane 0 transmit differential pair. Supports 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, and 5.4Gbps. All DisplayPort lanes transmit at the same data rate.
ML0N 38
ML1P 39 O DisplayPort Lane 1 transmit differential pair. Supports 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, and 5.4Gbps. All DisplayPort lanes transmit at the same data rate.
ML1N 40
ML2P 44 O DisplayPort Lane 2 transmit differential pair. Supports 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, and 5.4Gbps. All DisplayPort lanes transmit at the same data rate.
ML2N 45
ML3P 46 O DisplayPort Lane 3 transmit differential pair. Supports 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, and 5.4Gbps. All DisplayPort lanes transmit at the same data rate.
ML3N 47
AUXP 34 I/O Aux Channel Differential Pair.
AUXN 35
TEST1 60 I PD Test Mode. When high, the SN65DSIx6 enters Test Mode. This pin should be left unconnected or tied to ground for normal operation.
TEST2 55 I/O PD Used for internal test, HBR2 Compliance Eye, and Symbol Error Rate Measurement pattern. For normal operation, this pin should be pull-down to ground or left unconnected. Refer to DP Training and Compliance patterns for information on HBR2 Compliance Eye and Symbol Error Rate Measurement patterns.
TEST3 50 I Used for Texas Instruments internal use only. This pin must be left unconnected or tied to ground through a 0.1µF capacitor.
GPIO1 58 I/O General Purpose I/O. Refer to General Purpose Input and Outputs for details on GPIO functionality. When these pins are set high, they should be tied to the same 1.8V power rail where SN65DSIx6 VCCIO 1.8V power rail is connected.
GPIO2 56
GPIO3 54
GPIO4 57
HPD 32 I PD HPD Input. This input requires an 51K 1% series resistor.
ADDR 1 I Local I2C Interface Target Address Select. In normal operation, this pin is an input. When the ADDR pin is programmed high, it should be tied to the same 1.8V power rails where the SN65DSIx6 VCCIO 1.8V power rail is connected.
EN 2 I PU Chip Enable and Reset. Device is reset (shutdown) when EN is low.
REFCLK 51 I REFCLK. Frequency determined by value programmed in I2C register or value of GPIO[3:1] latched at rising edge of EN. Supported frequencies are: 12MHz, 19.2MHz, 26MHz, 27MHz, and 38.4MHz. This pin must be tied to or pulled down to ground when DACP/N feeds the DisplayPort PLL.
SCL 15 I Local I2C Interface Clock
SDA 16 I/O Local I2C Interface Data
IRQ 61 O Interrupt Signal
GND 23, 26, 52, 64,
Thermal pad		 G Reference Ground
VCCA 3, 14, 18, 31,
36, 41, 43, 48		 P 1.2V Power Supply for Analog Circuits.
VCCA and VCC must be applied simultaneously.
VCC 17, 33, 49, 59, 62 P 1.2V Power Supply for digital core
VPLL 42 P 1.8V Power Supply for DisplayPort PLL
VCCIO 53, 63 P 1.8V Power Supply for Digital I/O.