JAJSQ80C september   2013  – october 2020 SN65DSI86

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Description (continued)
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 54
          4. 8.4.5.7.4 Semi-Auto Link Training
          5. 8.4.5.7.5 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 76
          3. 9.2.1.2.3 DSI Design Procedure
          4. 9.2.1.2.4 78
          5. 9.2.1.2.5 Example Script
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
MIPI DSI INTERFACE
tGSDSI LP glitch suppression pulse width300ps
tHS-SETUPDSI HS data to clock setup time0.2UI
tHS-HOLDDSI HS clock to data hold time0.2UI
DisplayPort MAIN LINK
FBR7Bit rate 75.371385.45.40162Gbps
FBR6Bit rate 64.2971044.324.321296Gbps
FBR5Bit rate 53.2228283.243.240972Gbps
FBR4Bit rate 42.685692.72.70081Gbps
FBR3Bit rate 32.4171212.432.430729Gbps
FBR2Bit rate 22.1485522.162.160648Gbps
FBR1Bit rate 11.6114141.621.620486Gbps
UIBR7Unit interval for BR7High limit = +300 ppm.
Low limit = –5300 ppm
185ps
UIBR6Unit interval for BR6High limit = +300 ppm.
Low limit = –5300 ppm
231.5ps
UIBR5Unit interval for BR5High limit = +300 ppm.
Low limit = –5300 ppm
308.6ps
UIBR4Unit interval for BR4High limit = +300 ppm.
Low limit = –5300 ppm
370.4ps
UIBR3Unit interval for BR3High limit = +300 ppm.
Low limit = –5300 ppm
411.5ps
UIBR2Unit interval for BR2High limit = +300 ppm.
Low limit = –5300 ppm
463ps
UIBR1Unit interval for BR1High limit = +300 ppm.
Low limit = –5300 ppm
617.3ps
tERC_L0Differential output rise or fall time with DP_ERC set to 0506180ps
tERC_L1Differential output rise or fall time with DP_ERC set to 17495115ps
tERC_L2Differential output rise or fall time with DP_ERC set to 2108123146ps
tERC_L3Differential output rise or fall time with DP_ERC set to 3136153168ps
tTX_RISE_FALL
_MISMATCH
Lane intra-pair output skew at TX pins5%
tINTRA_SKEWIntra-pair differential skew20ps
tINTER_SKEWInter-pair differential skew100ps
tTX_EYE_HBR2Minimum TX eye width at TX package pins for HBR2(2)0.73UIHBR2
tTX_EYE_MED_TO
_MAX_JIT_HBR2
Maximum time between the jitter median and maximum deviation from the median at TX package pins for HBR2(2)0.135UIHBR2
tTX_EYE_HBRMinimum TX eye width at TX package pins for HBR(2)0.72UIHBR
tTX_EYE_MED_TO
_MAX_JIT_HBR
Maximum time between the jitter median and maximum deviation from the median at TX package pins for HBR(2)0.147UIHBR
tTX_EYE_RBRMinimum TX eye width at TX package pins for RBR(2)0.82UIRBR
tTX_EYE_MED_TO
_MAX_JIT_RBR
Maximum time between the jitter median and maximum deviation from the median at TX package pins for RBR(2)0.09UIRBR
tXSSC_AMPLink clock down-spreading0%0.5%
tSSC_FREQLink clock down-spreading frequency3033kHz
DisplayPort AUX INTERFACE
UIMANManchester transaction unit interval0.40.6µs
tauxjitter_txCycle-to-cycle jitter time at transmit pins0.08UIMAN
tauxjitter_rxCycle-to-cycle jitter time at receive pins0.04UIMAN
REFCLK
fREFCLKREFCLK frequency. supported frequencies: 12 MHz, 19.2 MHz, 26 MHz, 27 MHz, 38.4 MHz1238.4MHz
tRISEFALLREFCLK rise or fall time10% to 90%100 ps23ns
tREFCLKREFCLK period26.041783.333ns
tpjREFCLK peak-to-peak phase jitter50ps
DutyREFCLK duty cycle40%50%60%
All typical values are at VCC = 1.2 V and TA = 25 °C
BR refers to BR1; HBR refers to BR; HBR2 refers to BR7.
GUID-54F7DC2A-2807-4642-BDBB-298A95A5E805-low.gifFigure 7-1 Power-Up Timing Definitions for DPPLL_CLK_SRC = REFCLK
GUID-37E43621-E383-4631-A46D-B7E98DFB78C3-low.gifFigure 7-2 Power-Up Timing Definitions for DPPLL_CLK_SRC = DACP/N
GUID-95C8B4D8-F846-4500-A135-0CDE9D22E228-low.gifFigure 7-3 SUSPEND Timing Definitions
GUID-6BFCF470-07CE-4B6A-8930-16E34FF181EA-low.gifFigure 7-4 DSI HS Mode Receiver Timing Definitions
GUID-5601F974-FD79-4FF0-81BD-40AF09C49272-low.gifFigure 7-5 DSI Receiver Voltage Definitions