JAJSND7P February   2002  – February 2022 SN65HVD10 , SN65HVD11 , SN65HVD12 , SN75HVD10 , SN75HVD11 , SN75HVD12

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Power Dissipation Characteristics
    8. 7.8  Driver Switching Characteristics
    9. 7.9  Receiver Switching Characteristics
    10. 7.10 Dissipation Ratings
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low-Power Standby Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Fail-safe
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
      1. 12.3.1 Thermal Characteristics of IC Packages
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.9 Receiver Switching Characteristics

Over recommended operating conditions unless otherwise noted
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
tPLHPropagation delay time, low-to-high-level outputHVD10VID = –1.5 V to 1.5 V
CL = 15 pF
See Figure 8-9		12.52025ns
tPHLPropagation delay time, high-to-low-level outputHVD1012.52025
tPLHPropagation delay time, low-to-high-level outputHVD11 HVD12305570ns
tPHLPropagation delay time, high-to-low-level outputHVD11 HVD12305570ns
tsk(p)Pulse skew (|tPHL – tPLH|)HVD101.5ns
HVD114
HVD124
tsk(pp)(2)Part-to-part skewHVD108ns
HVD1115
HVD1215
trOutput signal rise timeCL = 15 pF
See Figure 8-9		125ns
tfOutput signal fall time125
tPZH(1)Output enable time to high levelCL = 15 pF, DE at 3 V
See Figure 8-10		15ns
tPZL(1)Output enable time to low level15
tPHZOutput disable time from high level20
tPLZOutput disable time from low level15
tPZH(2)Propagation delay time, standby-to-high-level outputCL = 15 pF, DE at 0
See Figure 8-11		6μs
tPZL(2)Propagation delay time, standby-to-low-level output6
(1) All typical values are at 25°C and with a 3.3-V supply
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.