SN65HVD11-HT 3.3-V RS-485 Transceiver
- SLLS934F November 2008 – November 2015 SN65HVD11-HT
  
  PRODUCTION DATA.

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DATA SHEET

SN65HVD11-HT 3.3-V RS-485 Transceiver

1 Features

Operates With a 3.3-V Supply
Bus-Pin ESD Protection Exceeds 16-kV Human-Body Model (HBM)
1/8 Unit-Load Option Available (up to 256 Nodes on Bus)
Optional Driver Output Transition Times for Signaling Rates ⁽¹⁾ of 1 Mbps, 10 Mbps, and
32 Mbps
Based on ANSI TIA/EIA-485-A
Bus-Pin Short Circuit Protection From
–7 V to 12 V
Open-Circuit, Idle-Bus, and Shorted-Bus Fail-Safe Receiver
Glitch-Free Power-Up and Power-Down Protection for Hot-Plugging Applications
SN75176 Footprint
Supports Extreme Temperature Applications:
- Controlled Baselines
- One Assembly and Test Sites
- One Fabrication Sites
- Available in Extreme (–55°C/210°C) Temperature Range ⁽²⁾
- Extended Product Life Cycles
- Extended Product-Change Notifications
- Product Traceability
- Texas Instruments' High Temperature Products Use Highly Optimized Silicon (Die) Solutions With Design and Process Enhancements to Maximize Performance Over Extended Temperatures.

(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bits per second (bps).

(2) Custom temperature ranges available

2 Applications

Down-Hole Drilling
High Temperature Environments
Digital Motor Controls
Utility Meters
Chassis-to-Chassis Interconnects
Electronic Security Stations
Industrial Process Controls
Building Automation
Point-of-Sale (POS) Terminals and Networks

3 Description

The SN65HVD11-HT device combines a 3-state differential line driver and differential input line receiver that operates with a single 3.3-V power supply. It is designed for balanced transmission lines and meets or exceeds ANSI TIA/EIA-485-A and ISO 8482:1993, with the exception that the thermal shutdown is removed. This differential bus transceiver is a monolithic integrated circuit designed for bidirectional data communication on multipoint bus-transmission lines. The driver and receiver have active-high and active-low enables, respectively, that can be externally connected together to function as direction control.

The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus when the driver is disabled or V_CC = 0.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SN65HVD11-HT	SOIC (8)	4.90 mm × 3.91 mm
	CFP (8) ⁽²⁾	6.90 mm × 5.65 mm
	CFP (8) ⁽³⁾	6.90 mm × 5.65 mm
	CDIP SB (8)	11.81 mm × 7.49 mm

For all available packages, see the orderable addendum at the end of the data sheet.
HKJ Package
HKQ Package

Typical Application Diagram

4 Revision History

Changes from E Revision (June 2012) to F Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

5 Pin Configuration and Functions

D, JD, or HKJ Package

8-Pin SOIC, PDIP, or CFP

Top View

HKQ Package

8-Pin CFP

Top View

Pin Functions

PIN			TYPE	DESCRIPTION
NAME	SOIC, PDIP	HKQ	TYPE	DESCRIPTION
A	6	6	Bus input/output	Driver output or receiver input (complementary to B)
B	7	7	Bus input/output	Driver output or receiver input (complementary to A)
D	4	4	Digital input	Driver data input
DE	3	3	Digital input	Active-high driver enable
GND	5	5	Reference potential	Local device ground
R	1	1	Digital output	Receive data output
RE	2	2	Digital input	Active-low receiver enable
V_CC	8	8	Supply	3-V to 3.6-V supply

Bare Die Information

DIE THICKNESS	BACKSIDE FINISH	BACKSIDE POTENTIAL	BOND PAD METALLIZATION COMPOSITION
15 mils.	Silicon with backgrind	GND	Cu-Ni-Pd

Bond Pad Coordinates in Microns - Rev A

DESCRIPTION⁽¹⁾	PAD NUMBER	a	b	c	d
R	1	69.3	372.15	185.3	489.15
~RE	2	388.75	71.5	503.75	186.5
DNC	3	722.4	55.4	839.4	172.4
DNC	4	891.4	55.4	1008.4	172.4
DE	5	1174.8	71.5	1289.8	186.5
DNC	6	1754.35	65.4	1869.35	180.4
DNC	7	1907.35	65.4	2022.35	180.4
D	8	2280.55	69.5	2395.55	184.5
DNC	9	2733.5	371.5	2848.5	486.5
GND	10	2691	1693.1	2808	1810.1
GND	11	2535	1693.1	2652	1810.1
DNC	12	2253.45	1685.65	2368.45	1800.65
A	13	1961.55	1693.1	2078.55	1810.1
B	14	799.55	1693.1	916.55	1810.1
DNC	15	498.35	1681.2	613.35	1796.2
VCC	16	244.8	1668.5	359.8	1783.5
VCC	17	91.8	1668.5	206.8	1783.5

(1) DNC = Do Not Connect

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage	–0.3	6	V
	Voltage at A or B	–9	14	V
	Input voltage at D, DE, R, or RE	–0.5	V_CC + 0.5	V
	Voltage input, transient pulse, A and B, through 100 Ω (see Figure 20)	–50	50	V
I_O	Receiver output current	–11	11	mA
	Continuous total power dissipation	See Thermal Information

(1) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	A, B, and GND	±16000	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins	±4000
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage		3		3.6	V
V_I or V_IC	Voltage at any bus terminal (separately or common-mode)		–7⁽¹⁾		12	V
V_IH	High-level input voltage	D, DE, RE	2		V_CC	V
V_IL	Low-level input voltage	D, DE, RE	0		0.8	V
V_ID	Differential input voltage	Figure 16	–12		12	V
I_OH	High-level output current	Driver	–60			mA
I_OH	High-level output current	Receiver	–8			mA
I_OL	Low-level output current	Driver			60	mA
I_OL	Low-level output current	Receiver			8	mA
R_L	Differential load resistance		54	60		Ω
C_L	Differential load capacitance			50		pF
	Signaling rate				10	Mbps
T_J⁽²⁾	Operating junction temperature	T_A = –55°C to 125°C		129		°C
		T_A = 175°C		179
		T_A = 210°C		214

(1) The algebraic convention, in which the least-positive (most-negative) limit is designated as minimum, is used in this data sheet.

(2) See Thermal Information table for information regarding this specification.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN65HVD11-HT				UNIT
		D (SOIC)	JD (CDIP SB)	HKJ (CFP)	HKQ (CFP)
		8 PINS	8 PINS	8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	101.5	73.9	N/A	170	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	53.6	N/A	N/A	6.2	°C/W
R_θJB	Junction-to-board thermal resistance	45.1	39.8	N/A	195	°C/W
ψ_JT	Junction-to-top characterization parameter	4.8	6.9	N/A	3.8	°C/W
ψ_JB	Junction-to-board characterization parameter	41.8	49.2	N/A	146.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	9.1	6.2	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Driver Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER			TEST CONDITIONS			MIN	TYP	MAX	UNIT
V_IK	Input clamp voltage		I_I = –18 mA			–1.5			V
\|V_OD\|	Differential output voltage		I_O = 0			2		V_CC	V
			R_L = 54 Ω, See Figure 10			1
			V_test = –7 V to 12 V, See Figure 11			1
Δ\|V_OD\|	Change in magnitude of differential output voltage		V_test = –7 V to 12 V, See Figure 10 and Figure 11			–0.2		0.2	V
V_OC(PP)	Peak-to-peak common mode output voltage		See Figure 12				400		mV
V_OC(SS)	Steady-state common mode output voltage		See Figure 12			1.4		2.5	V
ΔV_OC(SS)	Change in steady-state common mode output voltage		See Figure 12			–0.06		0.06	V
I_OZ	High-impedance output current		See receiver input currents
I_I	Input current	D		T_A = –55°C to 125°C		–100		0	μA
				T_A = 175°C⁽¹⁾		–100		3
				T_A = 210°C⁽²⁾		–100		3
		DE				0		100
I_OS	Short circuit output current		–7 V ≤ V_O ≤ 12 V			–250		250	mA
C_(OD)	Differential output capacitance		V_OD = 0.4 sin (4E6πt) + 0.5 V, DE = 0 V				18		pF
I_CC	Supply current		RE = V_CC, D and DE = V_CC, No load	Receiver disabled and driver enabled	T_A = –55°C to 125°C		11	15.5	mA
					T_A = 175°C⁽¹⁾		11.5	17.5
					T_A = 210°C⁽²⁾		14	18
			RE = V_CC, D = V_CC, DE = 0 V, No load	Receiver disabled and driver disabled (standby)	T_A = –55°C to 125°C		2.5	20	μA
					T_A = 175°C⁽¹⁾		20	150
					T_A = 210°C⁽²⁾		175	450
			RE = 0 V, D and DE = V_CC, No load	Receiver enabled and driver enabled	T_A = –55°C to 125°C		11	15.5	mA
					T_A = 175°C⁽¹⁾		11	17.5
					T_A = 210°C⁽²⁾		11	18

(1) Minimum and maximum parameters are characterized for operation at T_A = 175°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.

(2) Minimum and maximum parameters are characterized for operation at T_A = 210°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.

6.6 Receiver Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS			MIN	TYP	MAX	UNIT
V_IT+	Positive-going input threshold voltage	I_O = –8 mA					–0.01	V
V_IT–	Negative-going input threshold voltage	I_O = 8 mA			–0.2			V
V_hys	Hysteresis voltage (V_IT+ –V_IT–)		T_A = –55°C to 125°C			35		mV
			T_A = 175°C⁽¹⁾			41
			T_A = 210°C⁽²⁾			41
V_IK	Enable-input clamp voltage	I_I = –18 mA			–1.5			V
V_OH	High-level output voltage	V_ID = 200 mV, I_OH = –8 mA, See Figure 16			2.4			V
V_OL	Low-level output voltage	V_ID = –200 mV, I_OL = 8 mA, See Figure 16					0.4	V
I_OZ	High-impedance state output current	V_O = 0 or V_CC,RE = V_CC			–1		1	μA
I_I	Bus input current	V_A or V_B = 12 V	Other input at 0 V	T_A = –55°C to 125°C		0.075	0.11	mA
				T_A = 175°C⁽¹⁾		0.1	0.15
				T_A = 210°C⁽²⁾		0.1	0.15
		V_A or V_B = 12 V, V_CC = 0 V		T_A = –55°C to 125°C		0.085	0.13
				T_A = 175°C⁽¹⁾		0.12	0.16
				T_A = 210°C⁽²⁾		0.12	0.16
		V_A or V_B = –7 V		T_A = –55°C to 125°C	–0.1	–0.05
				T_A = 175°C⁽¹⁾	–0.3	–0.15
				T_A = 210°C⁽²⁾	–0.3	–0.15
		V_A or V_B = –7 V, V_CC = 0 V		T_A = –55°C to 125°C	–0.1	–0.05
				T_A = 175°C⁽¹⁾	–0.3	–0.15
				T_A = 210°C⁽²⁾	–0.3	–0.15
I_IH	High-level input current, RE	V_IH = 2 V		T_A = –55°C to 125°C	–30		0	μA
				T_A = 175°C⁽¹⁾	–30		3
				T_A = 210°C⁽²⁾	–30		3
I_IL	Low-level input current, RE	V_IL = 0.8 V			–30		0	μA
C_ID	Differential input capacitance	V_ID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V		T_A = –55°C to 125°C		15		pF
				T_A = 175°C⁽¹⁾		18
				T_A = 210°C⁽²⁾		18
I_CC	Supply current	RE = 0 V, D and DE = 0 V, No load	Receiver enabled and driver disabled	T_A = –55°C to 125°C		5	8	mA
				T_A = 175°C⁽¹⁾		7.5	8.5
				T_A = 210°C⁽²⁾		7.5	10
		RE = V_CC, D = V_CC, DE = 0 V, No load	Receiver disabled and driver disabled (standby)	T_A = –55°C to 125°C		2.5	20	μA
				T_A = 175°C⁽¹⁾		12.5	200
				T_A = 210°C⁽²⁾		175	450
		RE = 0 V, D and DE = V_CC, No load	Receiver enabled and driver enabled	T_A = –55°C to 125°C		11	15.5	mA
				T_A = 175°C⁽¹⁾		11.5	17.5
				T_A = 210°C⁽²⁾		14	18

6.7 Driver Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_PLH	Propagation delay time, low-to-high-level output	R_L = 54 Ω, C_L = 50 pF, See Figure 13		18	25	40	ns
t_PHL	Propagation delay time, high-to-low-level output			18	25	40	ns
t_r	Differential output signal rise time		T_A = –55°C to 125°C	10	21	30	ns
			T_A = 175°C⁽¹⁾	10	22	30
			T_A = 210°C⁽²⁾	10	22	30
t_f	Differential output signal fall time		T_A = –55°C to 125°C	10	21	30	ns
			T_A = 175°C⁽¹⁾	10	22	30
			T_A = 210°C⁽²⁾	10	22	30
t_sk(p)	Pulse skew (\|t_PHL – t_PLH\|)					2.5	ns
t_sk(pp)⁽³⁾	Part-to-part skew (t_PHL or t_PLH)					11	ns
t_PZH	Propagation delay time, high-impedance to high-level output	R_L = 110 Ω, RE = 0 V, See Figure 14				55	ns
t_PHZ	Propagation delay time, high-level to high-impedance output					55	ns
t_PZL	Propagation delay time, high-impedance to low-level output	R_L = 110 Ω, RE = 0 V, See Figure 15				55	ns
t_PLZ	Propagation delay time, low-level to high-impedance output					75	ns
t_PZH	Propagation delay time, standby to high-level output	R_L = 110 Ω, RE = 3 V, See Figure 14				6	μs
t_PZL	Propagation delay time, standby to low-level output	R_L = 110 Ω, RE = 3 V, See Figure 15				6	μs

(3) t_sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

6.8 Receiver Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_PLH	Propagation delay time, low-to-high-level output	V_ID = –1.5 V to 1.5 V, C_L = 15 pF, See Figure 17		30	55	70	ns
t_PHL	Propagation delay time, high-to-low-level output			30	55	70	ns
t_sk(p)	Pulse skew (\|t_PHL – t_PLH\|)					4	ns
t_sk(pp)⁽³⁾	Part-to-part skew					15	ns
t_r	Output signal rise time	C_L = 15 pF, See Figure 17	T_A = –55°C to 125°C	1	3	5	ns
			T_A = 175°C⁽¹⁾	1	4	5
			T_A = 210°C⁽²⁾	1	4	5
t_f	Output signal fall time		T_A = –55°C to 125°C	1	3	5	ns
			T_A = 175°C⁽¹⁾	1	4	5
			T_A = 210°C⁽²⁾	1	4	5
t_PZH⁽²⁾	Output enable time to high level	C_L = 15 pF, DE = 3 V, See Figure 18				15	ns
t_PZL⁽²⁾	Output enable time to low level					15	ns
t_PHZ	Output disable time from high level					20	ns
t_PLZ	Output disable time from low level					15	ns
t_PZH⁽³⁾	Propagation delay time, standby-to-high-level output	C_L = 15 pF, DE = 0, See Figure 19				6	μs
t_PZL⁽³⁾	Propagation delay time, standby-to-low-level output	C_L = 15 pF, DE = 0, See Figure 19				6	μs

xxx

1. See data sheet for absolute maximum and minimum recommended operating conditions.

2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).

3. The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the dominant failure mechanism affecting device wearout for the specific device process and design characteristics.

4. Wirebond fail mode applicable for D package only.

5. Wirebond life approaches 0 hours < 200°C which is only true of the HD device.

Figure 1. SN65HVD11SJD/SKGDA/SHKJ/SHKQ/HD
Operating Life Derating Chart