SLLS934F November   2008  – November 2015 SN65HVD11-HT

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Driver Electrical Characteristics
    6. 6.6 Receiver Electrical Characteristics
    7. 6.7 Driver Switching Characteristics
    8. 6.8 Receiver Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Standby Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

SN65HVD11-HT pmi_dr_circ_lls505.gif Figure 10. Driver VOD Test Circuit and Voltage and Current Definitions
SN65HVD11-HT pmi_dr_lls505.gif Figure 11. Driver VOD With Common Mode Loading Test Circuit
SN65HVD11-HT pmi_test_lls505.gif Figure 12. Test Circuit and Definitions for Driver Common Mode Output Voltage
SN65HVD11-HT pmi_dr_sw_lls505.gif Figure 13. Driver Switching Test Circuit and Voltage Waveforms
SN65HVD11-HT pmi_dr_hi_lls505.gif Figure 14. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
SN65HVD11-HT pmi_dr_low_lls505.gif Figure 15. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
SN65HVD11-HT pmi_rec_vo_lls505.gif Figure 16. Receiver Voltage and Current Definitions
SN65HVD11-HT pmi_rec_sw_lls505.gif Figure 17. Receiver Switching Test Circuit and Voltage Waveforms
SN65HVD11-HT pmi_rec_circ_lls505.gif Figure 18. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
SN65HVD11-HT pmi_rec_time_lls505.gif Figure 19. Receiver Enable Time From Standby (Driver Disabled)
SN65HVD11-HT pmi_vtest_lls505.gif Figure 20. Test Circuit, Transient Overvoltage Test
SN65HVD11-HT inp_outp_lls505.gif Figure 21. Equivalent Input and Output Schematic Diagrams