JAJSPH3I July 2003 – January 2023 SN65HVD1176 , SN75HVD1176
PRODUCTION DATA
The differential receiver of the SN65HVD1176 device is failsafe to invalid bus states caused by the following:
In any of these cases, the differential receiver will output a failsafe logic-high state so that the output of the receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input-indeterminate range does not include zero volts differential.
To comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input VID is more positive than +200 mV, and must output a low when VID is more negative than –200 mV. The receiver parameters that determine the fail-safe performance are VIT(+) and VIT(–).
As shown in GUID-D3E8E680-9405-4F30-AE81-F3BA62ACF02A.html#GUID-D3E8E680-9405-4F30-AE81-F3BA62ACF02A, differential signals more negative than –200 mV will always cause a low receiver output, and differential signals more positive than –20 mV will always cause a high receiver output. Thus, when the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of –20 mV, and the receiver output will be high.