JAJSPH3I July   2003  – January 2023 SN65HVD1176 , SN75HVD1176

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Supply Current
    7. 6.7 Power Dissipation
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
      1.      Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Receiver Failsafe
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
    3. 11.3 Related Links
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Receiver Failsafe

The differential receiver of the SN65HVD1176 device is failsafe to invalid bus states caused by the following:

  • Open bus conditions, such as a disconnected connector
  • Shorted bus conditions, such as cable damage shorting the twisted-pair together
  • Idle bus conditions that occur when no driver on the bus is actively driving

In any of these cases, the differential receiver will output a failsafe logic-high state so that the output of the receiver is not indeterminate.

Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input-indeterminate range does not include zero volts differential.

To comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input VID is more positive than +200 mV, and must output a low when VID is more negative than –200 mV. The receiver parameters that determine the fail-safe performance are VIT(+) and VIT(–).

As shown in GUID-D3E8E680-9405-4F30-AE81-F3BA62ACF02A.html#GUID-D3E8E680-9405-4F30-AE81-F3BA62ACF02A, differential signals more negative than –200 mV will always cause a low receiver output, and differential signals more positive than –20 mV will always cause a high receiver output. Thus, when the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of –20 mV, and the receiver output will be high.