JAJSMH9O august   2009  – july 2023 SN65HVD3082E , SN65HVD3085E , SN65HVD3088E , SN75HVD3082E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information, SN65HVD308xE
    5. 6.5  Thermal Information, SNx5HVD3082E
    6. 6.6  Electrical Characteristics: Driver
    7. 6.7  Electrical Characteristics: Receiver
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics: Driver
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Fail-safe
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Usage in an RS-485 Transceiver
        2. 9.2.2.2 Low-Power Shutdown Mode
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations for IC Packages
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tPLHPropagation delay time, low-to-high-level outputCL = 15 pF (see Figure 7-9)HVD3082E
HVD3085E		75200ns
HVD3086E100
tPHLPropagation delay time, high-to-low-level outputHVD3082E
HVD3085E		79200ns
HVD3088E100
tsk(p)Pulse skew (|tPHL – tPLH|)HVD3082E
HVD3085E		430ns
HVD3088E10
trOutput signal rise timeVID = –1.5 V to 1.5 V,
CL = 15 pF (see Figure 7-9)		1.53ns
tfOutput signal fall time1.83
tPZHOutput enable time to high levelCL = 15 pF,
DE at 3 V
(see Figure 7-10 and Figure 7-11)		HVD3082E
HVD3085E		550ns
HVD3088E30
tPZLOutput enable time to low levelHVD3082E
HVD3085E		1050ns
HVD3088E30
tPHZOutput enable time from high levelHVD3082E
HVD3085E		550ns
HVD3088E30
tPLZOutput disable time from low levelHVD3082E
HVD3085E		850ns
HVD3088E30
tPZH(SHDN)Propagation delay time,
shutdown-to-high-level output		CL = 15 pF, DE at 0 V,
(see Figure 7-12)		16003500ns
tPZL(SHDN)Propagation delay time,
shutdown-to-low-level output		17003500