JAJSO03D November   2011  – April 2022 SN65HVDA100-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 概要 (続き)
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1) (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 17
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  LIN (Local Interconnect Network) Bus
        1. 9.3.1.1 LIN Transmitter Characteristics
        2. 9.3.1.2 LIN Receiver Characteristics
          1. 9.3.1.2.1 Termination
      2. 9.3.2  TXD (Transmit Input / Output)
      3. 9.3.3  RXD (Receive Output)
      4. 9.3.4  VSUP (Supply Voltage)
      5. 9.3.5  GND (Ground)
      6. 9.3.6  EN (Enable Input)
      7. 9.3.7  NWake (High Voltage Wake Up Input)
      8. 9.3.8  INH (Inhibit Output)
      9. 9.3.9  TXD Dominant State Timeout
      10. 9.3.10 Thermal Shutdown
      11. 9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout
      12. 9.3.12 Undervoltage on VSUP
      13. 9.3.13 Unpowered Device Does Not Affect the LIN Bus
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating States
      2. 9.4.2 Normal Mode
      3. 9.4.3 Sleep Mode
      4. 9.4.4 Wake-Up Events
        1. 9.4.4.1 Wake-Up Request (RXD)
        2. 9.4.4.2 Wake-Up Source Recognition (TXD)
      5. 9.4.5 Standby Mode
      6. 9.4.6 Mode Transitions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.2 Detailed Design Procedure

The RXD output structure is an open-drain output stage. This allows the SN65HVDA100-Q1 to be used with 3.3-V and 5-V I/O microcontrollers. If the RXD pin of the microcontroller does not have an integrated pullup, an external pullup resistor to the microcontroller I/O supply voltage is required.

The VSUP pin of the device should be decoupled with a 100-nF capacitor as close to the supply pin of the device as possible.

The NWAKE pin is a high voltage wake-up input to the device. If this pin is not being used it should be tied to VSUP.