JAJSO03D November   2011  – April 2022 SN65HVDA100-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 概要 (続き)
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1) (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 17
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  LIN (Local Interconnect Network) Bus
        1. 9.3.1.1 LIN Transmitter Characteristics
        2. 9.3.1.2 LIN Receiver Characteristics
          1. 9.3.1.2.1 Termination
      2. 9.3.2  TXD (Transmit Input / Output)
      3. 9.3.3  RXD (Receive Output)
      4. 9.3.4  VSUP (Supply Voltage)
      5. 9.3.5  GND (Ground)
      6. 9.3.6  EN (Enable Input)
      7. 9.3.7  NWake (High Voltage Wake Up Input)
      8. 9.3.8  INH (Inhibit Output)
      9. 9.3.9  TXD Dominant State Timeout
      10. 9.3.10 Thermal Shutdown
      11. 9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout
      12. 9.3.12 Undervoltage on VSUP
      13. 9.3.13 Unpowered Device Does Not Affect the LIN Bus
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating States
      2. 9.4.2 Normal Mode
      3. 9.4.3 Sleep Mode
      4. 9.4.4 Wake-Up Events
        1. 9.4.4.1 Wake-Up Request (RXD)
        2. 9.4.4.2 Wake-Up Source Recognition (TXD)
      5. 9.4.5 Standby Mode
      6. 9.4.6 Mode Transitions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VSUP = 5V to 27 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
VSUP SUPPLY
VSUPOperational supply voltage (ISO 17987-4 Param 10)(2)51427V
VSUPNominal supply voltage (ISO 17987-4 Param 10)Normal and standby modes71418V
Sleep mode71218
UVSUPUndervoltage VSUP threshold4.354.65V
UVHYSDelta hysteresis voltage for VSUP undervoltage threshold0.2V
ISUPSupply currentNormal mode, EN = high, Bus dominant (total bus load where RLIN ≥ 500 Ω and CLIN ≤ 10 nF (see Figure 8-1 )(3), INH = VSUP, NWake = VSUP1.27.5mA
Standby mode, EN = low, Bus dominant (total bus load where RLIN ≥ 500 Ω and CLIN ≤ 10 nF (see Figure 8-1)(3), INH = VSUP, NWake = VSUP12.1mA
Normal mode, EN = high, Bus recessive, LIN = VSUP, INH = VSUP, NWake = VSUP450775μA
Standby mode, EN = low, Bus recessive, LIN = VSUP, INH = VSUP, NWake = VSUP450775μA
Sleep mode, 7 V < VSUP ≤ 14 V,
LIN = VSUP, NWake = VSUP, EN = 0 V, TXD and RXD floating		1020μA
Sleep mode, 14 V < VSUP < 27 V,
LIN = VSUP, NWake = VSUP, EN = 0 V, TXD and RXD floating		30μA
RXD OUTPUT PIN (OPEN DRAIN)
VOOutput voltage(4)–0.35.5V
IOLLow-level output current, open drainLIN = 0 V, RXD = 0.4 V3.5mA
IIKGLeakage current, high-levelLIN = VSUP, RXD = 5 V–505μA
TXD INPUT/OUTPUT PIN
VILLow-level input voltage–0.30.8V
VIHHigh-level input voltage25.5V
VITInput threshold hysteresis voltage30500mV
Pulldown resistor125350800kΩ
IILLow-level input leakage currentTXD = Low–505μA
ITXD_WakeLocal wake up source re recognition TXD open drain driveStandby mode after a local wake up event, VLIN = VSUP, NWake = 0 V,
TXD = 1 V		1.34.68mA
LIN PIN (REFERENCED TO VSUP)
VOHHigh-level output voltageLIN recessive, TXD = high, IO = 0 mA,
VSUP = 14 V		VSUP – 1V
VOLLow-level output voltageLIN dominant, TXD = low, IO = 40 mA,
VSUP = 14 V		0.2 × VSUPV
ILLimiting current (ISO 17987-4 Param 12)TXD = 0 V, VLIN = 7 V to 27 V4090200mA
ILKGReceiver leakage current, dominant (ISO 17987-4 Param 13)LIN = 0 V, 7 V ≤VSUP ≤ 18 V, Driver off–1mA
Receiver leakage current, recessive (ISO 17987-4 Param 14)LIN ≥ VSUP, 7 ≤ VSUP ≤18 V, Driver off20μA
LIN = VSUP, driver off–55
ILKGLeakage current, loss of ground (ISO 17987-4 Param 15)GND = VSUP , VSUP = 12 V,
0 V < VLIN < 18 V		–11mA
ILKGLeakage current, loss of supply (ISO 17987-4 Param 16)7 V < LIN ≤ 12 V, VSUP = GND5μA
12 V < LIN ≤ 18 V, VSUP = GND10
VILLow-level input voltage (ISO 17987-4 Param 17)LIN dominant (including LIN dominant for wake up)0.4 × VSUPV
VIHHigh-level input voltage (ISO 17987-4 Param 18)LIN recessive0.6 × VSUPV
VBUS_CNTReceiver center threshold (ISO 17987-4 Param 19)VBUS_CNT = (VIL + VIH) / 20.475 x VSUP0.5 × VSUP0.525 x VSUPV
VHYSHysteresis voltage (ISO 17987-4 Param 20)VHYS = (VIL - VIH)0.05 × VSUP0.175 × VSUPV
VSERIAL_ DIODESerial diode in LIN termination pull up path (ISO 17987-4 Param 21)By design and characterization0.40.71.0V
RRESPONDERPullup resistor to VSUP (ISO 17987-4 Param 26)Normal and standby modes203060kΩ
RSLEEPPullup current source to VSUPSleep mode, VSUP = 14 V, LIN = GND–2–20μA
EN INPUT PIN
VILLow-level input voltage–0.30.8V
VIHHigh-level input voltage25.5V
VhysHysteresis voltageBy design and characterization30500mV
Pulldown resistor125350800kΩ
IILLow-level input currentEN = Low–505μA
INH OUTPUT PIN
RDS(on)ON-state resistanceBetween VSUP and INH, INH = 2-mA drive, Normal or standby mode2550Ω
IIKGLeakage currentLow-power mode, 0 < INH < VSUP–505μA
NWAKE INPUT PIN
VILLow-level input voltage–0.3VSUP – 3.3V
VIHHigh-level input voltageVSUP – 1VSUP + 0.3V
Pullup currentNWake = 0 V–45–10–2μA
IIKGLeakage currentVSUP = NWake–505μA
AC CHARACTERISTICS
D1Duty cycle 1(5) (ISO 17987-4 Param 27)THREC(max) = 0.744 × VSUP, THDOM(maximum) = 0.581 × VSUP,
VSUP = 7 V to 18 V, tBIT = 50 μs (20 kbps),
D1 = tBus_rec(min)/ (2 × tBIT) (see Figure 7-1)		0.396
D2Duty cycle 2(5) (ISO 17987-4 Param 28)THREC(min) = 0.422 × VSUP,
THDOM(min) = 0.284 × VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 50 μs (20 kbps),
D2 = tBus_rec(max)/ (2 × tBIT) (see Figure 7-1)		0.581
D3Duty cycle 3(5) (ISO 17987-4 Param 29)THREC(max) = 0.778 × VSUP,
THDOM(max) = 0.616 × VSUP,
VSUP = 7 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D3 = tBus_rec(min)/ (2 × tBIT) (see Figure 7-1)		0.417
D4Duty cycle 4(5) (ISO 17987-4 Param 30)THREC(min) = 0.389 × VSUP,
THDOM(min) = 0.251 × VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D4 = tBus_rec(max)/ (2 × tBIT) (see Figure 7-1)		0.59
(1) Typical values are given for VSUP = 14 V at 25°C, except for low power mode where typical values are given for VSUP = 12 V at 25°C.
(2) All voltages are defined with respect to ground; positive currents flow into the SN65HVDA100-Q1 device.
(3) In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN responder termination resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN responder termination is 20 kΩ, so the maximum supply current attributed to the termination is:ISUP (dom) max termination ≉ (VSUP – (VLIN_Dominant + 0.7 V) / 20 kΩ.
(4) RXD pin output is open drain. Output voltage is through external pullup resistance to logic supply of the system and impedance of the RXD pin.
(5) Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are defined for 10.4-kbps operation. The SN65HVDA100-Q1 also meets these lower data rate requirements, while it is capable of the higher speed 20-kbps operation as specified by duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions, for details see the SAEJ2602 specification.