JAJSL15N July   1997  – April 2021 SN55LVDS31 , SN65LVDS31 , SN65LVDS3487 , SN65LVDS9638

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings #GUID-35E89C88-1E48-404C-8AB6-22CCA817C2ED/SLLS2613609
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: SN55LVDS31
    6. 7.6 Electrical Characteristics: SN65LVDSxxxx
    7. 7.7 Switching Characteristics: SN55LVDS31
    8. 7.8 Switching Characteristics: SN65LVDSxxxx
    9. 7.9 Typical Characteristics
      1. 7.9.1 17
  8. 8 Parameter Measurement Information
    1. 8.1 19
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Driver Disabled Output
      2. 9.3.2 NC Pins
      3. 9.3.3 Unused Enable Pins
      4. 9.3.4 Driver Equivalent Schematics
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Point-to-Point Communications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Driver Supply Voltage
          2. 10.2.1.2.2 Driver Bypass Capacitance
          3. 10.2.1.2.3 Driver Output Voltage
          4. 10.2.1.2.4 Interconnecting Media
          5. 10.2.1.2.5 PCB Transmission Lines
          6. 10.2.1.2.6 Termination Resistor
          7. 10.2.1.2.7 Driver NC Pins
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Multidrop Communications
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Interconnecting Media
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 49
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip vs. Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Other LVDS Products
    2. 13.2 Documentation Support
      1. 13.2.1 Related Information
      2. 13.2.2 ドキュメントの更新通知を受け取る方法
      3. 13.2.3 Related Links
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

7.6 Electrical Characteristics: SN65LVDSxxxx

over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSSN65LVDS31
SN65LVDS3487
SN65LVDS9638		UNIT
MINTYP(1)MAX
VODDifferential output voltage magnitudeRL = 100 Ω, See Figure 8-2247340454mV
ΔVODChange in differential output voltage magnitude between logic statesRL = 100 Ω, See Figure 8-2–5050mV
VOC(SS)Steady-state common-mode output voltageSee Figure 8-31.1251.21.375V
ΔVOC(SS)Change in steady-state common-mode output voltage between logic statesSee Figure 8-3–5050mV
VOC(PP)Peak-to-peak common-mode output voltageSee Figure 8-350150mV
ICCSupply currentSN65LVDS31
SN65LVDS3487		VI = 0.8 V or 2 V, Enabled, No load920mA
VI = 0.8 or 2 V, RL = 100 Ω, Enabled2535
VI = 0 or VCC, Disabled0.251
SN65LVDS9638VI = 0.8 V or 2 VNo load4.78mA
RL = 100 Ω913
IIHHigh-level input currentVIH = 2420μA
IILLow-level input currentVIL = 0.8 V0.110μA
IOSShort-circuit output currentVO(Y) or VO(Z) = 0–4–24mA
VOD = 0±12
IOZHigh-impedance output currentVO = 0 or 2.4 V±1μA
IO(OFF)Power-off output currentVCC = 0, VO = 2.4 V±1μA
CiInput capacitance3pF
(1) All typical values are at TA = 25°C and with VCC = 3.3 V.