DATA SHEET
SN65LVDS4 1.8-V High-Speed Differential Line Receiver
1 Features
- Designed for Signaling Rates up to: (1)
- Operates From a 1.8-V or 2.5-V Core Supply
- Available in 1.5-mm × 2-mm UQFN Package
- Bus-Terminal ESD Exceeds 2 kV (HBM)
- Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV Into a 100-Ω Load
- Propagation Delay Times
- 2.1 ns Typical Receiver
- Power Dissipation at 250 MHz
- 40 mW Typical
- Requires External Failsafe
- Differential Input Voltage Threshold Less Than 50 mV
- Can Provide Output Voltage Logic Level (3.3-V LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based on External VDD Pin, Thus Eliminating External Level Translation
(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second)
2 Applications
- Clock Distribution
- Wireless Base Stations
- Network Routers
3 Description
The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN65LVDS4 | UQFN (10) | 1.50 mm × 2.00 mm |
- For all available packages, see the orderable addendum at the end of the datasheet.
Typical Application Circuits
4 Revision History
Changes from * Revision (July 2011) to A Revision
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
5 Pin Configuration and Functions
RSE Package
10-Pin UQFN
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| A | 2 | I | LVDS input, positive |
| B | 3 | I | LVDS input, negative |
| GND | 1, 7 | – | Ground |
| NC | 4, 6, 9 | – | No connect |
| R | 8 | O | 1.8/2.5 LVCMOS/3.3 LVTTL output |
| VCC | 5 | – | Core supply voltage |
| VDD | 10 | – | Output drive voltage |
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage range, VCC (2) | –0.5 | 4 | V | |
| Receiver output voltage logic level and driver input voltage logic level supply, VDD | –0.5 | 4 | V | |
| Input voltage range, VI | (A or B) | –0.5 | VCC + 0.3 | V |
| Output voltage, VO | (R) | –0.5 | VDD + 0.3 | V |
| Differential input voltage magnitude, |VID| | 1 | V | ||
| Receiver output current, IO | –12 | 12 | mA | |
| Continuous total power dissipation, PD | See Thermal Information | |||
| Storage temperature (non operating) | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
6.2 ESD Ratings
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins | 2000 | V |
| Bus pins (A, B, Y, Z) | 2000 | ||||
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | 500 | ||||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VCC1.8 | Core supply voltage | 1.62 | 1.8 | 1.98 | V |
| VCC2.5 | Core supply voltage | 2.25 | 2.5 | 2.75 | V |
| VDD1.8 | Output drive voltage | 1.62 | 1.8 | 1.98 | V |
| VDD2.5 | Output drive voltage | 2.25 | 2.5 | 2.75 | V |
| VDD3.3 | Output drive voltage | 3 | 3.3 | 3.6 | V |
| TA | Operating free-air temperature | –40 | 85 | °C | |
| |VID| | Magnitude of differential input voltage | 0.15 | 0.6 | V | |
| fop | Operating frequency range | 10 | 250 | MHz | |
| |VINMAX| | Input voltage (any combination of input or common-mode voltage) See (1)Maximum Input Voltage, VIN(max). | 0 | VCC | V | |
(1) Any combination of input or common-mode voltage should not be below 0 V or above VCC.
6.4 Thermal Information
| THERMAL METRIC(1) | SN65LVDS4 | UNIT | |
|---|---|---|---|
| RSE (UQFN) | |||
| 10 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 171.2 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 60.7 | °C/W |
| RθJB | Junction-to-board thermal resistance | 71.4 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.8 | °C/W |
| ψJB | Junction-to-board characterization parameter | 64.7 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Receiver Electrical Characteristics: VCC = 2.5 V
over recommended operating conditions, VCC = 2.5 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN(2) | TYP(1) | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| VITH+ | Positive-going differential input voltage threshold | See Figure 17, VCC1.8 , VCC2.5 | 50 | mV | |||
| VITH– | Negative-going differential input voltage threshold | See Figure 17, VCC1.8 , VCC2.5 | –50 | mV | |||
| VOH | High-level output voltage | VDD = 3.3 V, IOH = –8 mA | VDD – 0.25 | V | |||
| VDD = 2.5 V, IOH = –6 mA | VDD – 0.25 | ||||||
| VDD = 1.8 V, IOH = –4 mA | VDD – 0.25 | ||||||
| VOL | Low-level output voltage | VDD = 3.3 V, IOL = 8 mA | 0.25 | V | |||
| VDD = 2.5 V, IOL = 6 mA | 0.25 | ||||||
| VDD = 1.8 V, IOL = 4 mA | 0.25 | ||||||
| Pstatic | Static power | No load, steady state, VDD = 3.3 V, VID+ | 22 | 28 | mW | ||
| No load, steady state, VDD = 2.5 V, VID+ | 20 | 25 | |||||
| CI | Input capacitance | VI = 0.4 sin(4E6πt) + 0.5 V | 4 | pF | |||
| CO | Output capacitance | VI = 0.4 sin(4E6πt) + 0.5 V | 4 | pF | |||
(1) All typical values are at 25°C .
(2) The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet.
6.6 Receiver Electrical Characteristics: VCC = 1.8 V
over recommended operating conditions, VCC = 1.8 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN(2) | TYP(1) | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| VITH+ | Positive-going differential input voltage threshold | See Figure 17, VCC1.8 , VCC2.5 | 50 | mV | |||
| VITH– | Negative-going differential input voltage threshold | See Figure 17, VCC1.8 , VCC2.5 | –50 | mV | |||
| VOH | High-level output voltage | VDD = 3.3 V, IOH = –8 mA | VDD – 0.25 | V | |||
| VDD = 2.5 V, IOH = –6 mA | VDD – 0.25 | ||||||
| VDD = 1.8 V, IOH = –4 mA | VDD – 0.25 | ||||||
| VOL | Low-level output voltage | VDD = 3.3 V, IOL = 8 mA | 0.25 | V | |||
| VDD = 2.5 V, IOL = 6 mA | 0.25 | ||||||
| VDD = 1.8 V, IOL = 4 mA | 0.25 | ||||||
| Pstatic | Static power | No load, steady state, VDD = 3.3 V, VID+ | 18 | 21 | mW | ||
| No load, steady state, VDD = 2.5 V, VID+ | 16 | 19 | |||||
| No load, steady state, VDD = 1.8 V, VID+ | 13 | 16 | |||||
| CI | Input capacitance | VI = 0.4 sin(4E6πt) + 0.5 V | 4 | pF | |||
| CO | Output capacitance | VI = 0.4 sin(4E6πt) + 0.5 V | 4 | pF | |||
6.7 Receiver Switching Characteristics: VCC = 2.5 V
over recommended operating conditions, VCC = 2.5 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| tPLH | Propagation delay time, low-to-high-level output | CL = 10 pF, See Figure 19 |
2.5 | 3.3 | ns | ||
| tPHL | Propagation delay time, high-to-low-level output | 2.5 | 3.3 | ns | |||
| tsk(p) | Pulse skew (|tpHL – tpLH|)(2) | 240 | ps | ||||
| tr | Output signal rise time | VDD = 3.3 V | 550 | ps | |||
| VDD = 2.5 V | 600 | ||||||
| tf | Output signal fall time | VDD = 3.3 V | 550 | ps | |||
| VDD = 2.5 V | 600 | ||||||
| tjit | Residual jitter added | Carrier frequency = 122.8 MHz, input signal amplitude = 500 mVpp sine wave, integration bandwidth for rms jitter = 20 khz-20 MHz, VDD = 2.5 V | 370 | fs | |||
(1) All typical values are at 25°C.
(2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
6.8 Receiver Switching Characteristics: VCC = 1.8 V
over recommended operating conditions, VCC = 1.8 V, VID = 150 mV–600 mV, VCM = VID/2 to VCC – VID/2 V, 10 pF load (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| tPLH | Propagation delay time, low-to-high-level output | CL = 10 pF, See Figure 19 |
3.2 | 3.8 | ns | ||
| tPHL | Propagation delay time, high-to-low-level output | 3.2 | 3.8 | ns | |||
| tsk(p) | Pulse skew (|tpHL – tpLH|)(2) | 240 | ps | ||||
| tr | Output signal rise time | VDD = 3.3 V | 550 | ps | |||
| VDD = 2.5 V | 600 | ||||||
| VDD = 1.8 V | 750 | ||||||
| tf | Output signal fall time | VDD = 3.3 V | 550 | ps | |||
| VDD = 2.5 V | 600 | ||||||
| VDD = 1.8 V | 750 | ||||||
| tjit | Residual jitter added | Carrier frequency = 122.8 MHz, input signal amplitude = 500 mVpp sine wave, integration bandwidth for rms jitter = 20 khz-20 MHz, VDD = 1.8 V | 370 | fs | |||
6.9 Typical Characteristics
VICM = 1.2 V, VID = 300 mV, CL = 10 pF, input rise time and fall time = 1 ns, input frequency = 250 MHz, 50% duty cycle, TA = 25°C, unless otherwise noted
Figure 1. High-Level Output Voltage vs. High-Level Output Current
Figure 3. High- to Low-Level Propagation Delay Time vs. Free-Air Temperature
Figure 5. Rise Time vs. Capacitive Load
Figure 7. Supply Current vs. Frequency
Figure 9. Pulse Skew vs. Temperature
Figure 11. Pulse Skew vs. Differential Input Voltage
Figure 13. Propagation Delay, Low-to-High vs. Differential Input Voltage
Figure 15. Propagation Delay, High-to-Low vs. Differential Input Voltage
Figure 2. Low-Level Output Voltage vs. Low-Level Output Current
Figure 4. Low- to High-Level Propagation Delay Time vs. Free-Air Temperature
Figure 6. Fall Time vs. Capacitive Load
Figure 8. Supply Current vs. Temperature
Figure 10. Pulse Skew vs. Common-Mode Voltage
Figure 12. Propagation Delay, Low-to-High vs. Common-Mode Voltage
Figure 14. Propagation Delay, High-to-Low vs. Common-Mode Voltage
Figure 16. Power vs. Frequency
