SN65LVDS4 1.8-V High-Speed Differential Line Receiver

1 Features

Designed for Signaling Rates up to:
- 500-Mbps Receiver
⁽¹⁾
Operates From a 1.8-V or 2.5-V Core Supply
Available in 1.5-mm × 2-mm UQFN Package
Bus-Terminal ESD Exceeds 2 kV (HBM)
Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV Into a 100-Ω Load
Propagation Delay Times
- 2.1 ns Typical Receiver
Power Dissipation at 250 MHz
- 40 mW Typical
Requires External Failsafe
Differential Input Voltage Threshold Less Than 50 mV
Can Provide Output Voltage Logic Level (3.3-V LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based on External VDD Pin, Thus Eliminating External Level Translation

(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second)

The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package.

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SN65LVDS4	UQFN (10)	1.50 mm × 2.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Changes from * Revision (July 2011) to A Revision

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

RSE Package

10-Pin UQFN