JAJSTH2B July   2006  – March 2024 SN65MLVD047A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Package Dissipation Ratings
    5. 5.5 Thermal Information
    6. 5.6 Device Electrical Characteristics
    7. 5.7 Device Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Synchroization Clock in AdvancedTCA
      2. 8.1.2 Multipoint Configuration
      3. 8.1.3 Multidrop Configuration
      4. 8.1.4 Unused Channel
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.7 Device Electrical Characteristics

over recommended operating conditions unless otherwise noted
PARAMETERTEST CONDITIONSMIN(1)TYP(2)MAXUNIT
LVTTL (EN, EN, 1A:4A)
|IIH|High-level input currentVIH = 2 V or VCC010μA
|IIL|Low-level input currentVIL = GND or 0.8 V010μA
CiInput capacitanceVI = 0.4 sin(30E6πt) + 0.5 V(3)5pF
M-LVDS (1Y/1Z:4Y/4Z)
|VYZ|Differential output voltage magnitudeSee Figure 6-2480650mV
Δ|VYZ|Change in differential output voltage magnitude between logic states–5050mV
VOS(SS)Steady-state common-mode output voltageSee Figure 6-30.81.2V
ΔVOS(SS)Change in steady-state common-mode output voltage between logic states–5050mV
VOS(PP)Peak-to-peak common-mode output voltage150mV
VY(OC)Maximum steady-state open-circuit output voltageSee Figure 6-702.4V
VZ(OC)Maximum steady-state open-circuit output voltage02.4V
VP(H)Voltage overshoot, low-to-high level outputSee Figure 6-51.2 VSSV
VP(L)Voltage overshoot, high-to-low level output–0.2 VSSV
|IOS|Differential short-circuit output current magnitudeSee Figure 6-424mA
IOZHigh-impedance state output current–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
Other output = 1.2 V		–1510μA
IO(OFF)Power-off output current–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
Other output = 1.2 V, VCC = 0 V		–1010μA
CY or CZOutput capacitanceVY or VZ = 0.4 sin(30E6πt) + 0.5 V,(3)
Other input at 1.2 V, driver disabled		3pF
CYZDifferential output capacitanceVYZ = 0.4 sin(30E6πt) V,(3)
Driver disabled		2.5pF
CY/ZOutput capacitance balance, (CY/CZ)0.991.01
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)