SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates
- SDLS025D December 1983 – May 2017 SN5400 , SN54LS00 , SN54S00 , SN7400 , SN74LS00 , SN74S00
  
  PRODUCTION DATA.

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DATA SHEET

SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates

1 Features

Package Options Include:
- Plastic Small-Outline (D, NS, PS)
- Shrink Small-Outline (DB)
- Ceramic Flat (W)
- Ceramic Chip Carriers (FK)
- Standard Plastic (N)
- Ceramic (J)
Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package
Inputs Are TTL Compliant; V_IH = 2 V and
V_IL = 0.8 V
Inputs Can Accept 3.3-V or 2.5-V Logic Inputs
SN5400, SN54LS00, and SN54S00 are Characterized For Operation Over the Full Military Temperature Range of –55ºC to 125ºC

2 Applications

AV Receivers
Portable Audio Docks
Blu-Ray Players
Home Theater
MP3 Players or Recorders
Personal Digital Assistants (PDAs)

3 Description

The SNx4xx00 devices contain four independent,
2-input NAND gates. The devices perform the Boolean function Y = A .B or Y = A + B in positive logic.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SN74LS00DB	SSOP (14)	6.20 mm × 5.30 mm
SN7400D, SN74LS00D, SN74S00D	SOIC (14)	8.65 mm × 3.91 mm
SN74LS00NSR	PDIP (14)	19.30 × 6.35 mm
SNJ5400J, SNJ54LS00J, SNJ54S00J	CDIP (14)	19.56 mm × 6.67 mm
SNJ5400W, SNJ54LS00W, SNJ54S00W	CFP (14)	9.21 mm × 5.97 mm
SN54LS00FK, SN54S00FK	LCCC (20)	8.89 mm × 8.89 mm
SN7400NS, SN74LS00NS, SN74S00NS	SO (14)	10.30 mm × 5.30 mm
SN7400PS, SN74LS00PS	SO (8)	6.20 mm × 5.30 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram, Each Gate (Positive Logic)

SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00 ld_cas279.gif

4 Revision History

Changes from C Revision (November 2016) to D Revision

Changed Typical Application Diagram see Application and Implementation section.Go

Changes from B Revision (October 2003) to C Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
Changed Ordering Information table to Device Comparison Table; see Package Option Addendum at the end of the data sheetGo
Changed Package thermal impedance, R_θJA, values in Thermal Information table From: 86°C/W To: 90.9°C/W (D), From: 96°C/W To: 102.8°C/W (DB), From: 80°C/W To: 54.8°C/W (N), and From: 76°C/W To: 89.7°C/W (NS)Go

5 Pin Configuration and Functions

SN5400 J, SN54xx00 J and W, SN74x00 D, N, and NS, or SN74LS00 D, DB, N, and NS Packages

14-Pin CDIP, CFP, SOIC, PDIP, SO, or SSOP

Top View

SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00 D_sop_pin_diagram.gif

SN5400 W Package

14-Pin CFP

Top View

SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00 W_sop_pin_diagram.gif

SN74xx00 PS Package

18-Pin SO

Top View

SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00 PS_sop_pin_diagram.gif

SN54xx00 FK Package

20-Pin LCCC

Top View

SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00 FK_fk_pin_diagram.gif

Pin Functions

PIN					I/O	DESCRIPTION
NAME	CDIP, CFP, SOIC, PDIP, SO, SSOP	SO (SN74xx00)	CFP (SN5400)	LCCC	I/O	DESCRIPTION
1A	1	1	1	2	I	Gate 1 input
1B	2	2	2	3	I	Gate 1 input
1Y	3	3	3	4	O	Gate 1 output
2A	4	6	6	6	I	Gate 2 input
2B	5	7	7	8	I	Gate 2 input
2Y	6	5	5	9	O	Gate 2 output
3A	10	—	9	13	I	Gate 3 input
3B	9	—	10	14	I	Gate 3 input
3Y	8	—	8	12	O	Gate 3 output
4A	13	—	12	18	I	Gate 4 input
4B	12	—	13	19	I	Gate 4 input
4Y	11	—	14	16	O	Gate 4 output
GND	7	4	11	10	—	Ground
NC	—	—	—	1, 5, 7, 11, 15, 17	—	No connect
V_CC	14	8	4	20	—	Power supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage, V_CC⁽²⁾			7	V
Input voltage	SNx400 and SNxS400		5.5	V
Input voltage	SNx4LS00		7	V
Junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltage values are with respect to network ground terminal.

6.2 ESD Ratings: SN74LS00

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance. ESD Tested on SN74LS00N package.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage	SN54xx00	4.5	5	5.5	V
V_CC	Supply voltage	SN74xx00	4.75	5	5.25	V
V_IH	High-level input voltage		2			V
V_IL	Low-level input voltage	SNx400, SN7LS400, and SNx4S00			0.8	V
V_IL	Low-level input voltage	SN54LS00			0.7	V
I_OH	High-level output current	SN5400, SN54LS00, and SN74LS00			–0.4	mA
I_OH	High-level output current	SNx4S00			–1	mA
I_OL	Low-level output current	SNx400			16	mA
		SN5LS400			4
		SN7LS400			8
		SNx4S00			20
T_A	Operating free-air temperature	SN54xx00	–55		125	°C
T_A	Operating free-air temperature	SN74xx00	0		70	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		SN74LS00				UNIT
		D (SOIC)	DB (SSOP)	N (PDIP)	NS (SO)
		14 PINS	14 PINS	14 PINS	14 PINS
R_θJA	Junction-to-ambient thermal resistance	90.9	102.8	54.8	89.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	51.9	53.3	42.1	48.1	°C/W
R_θJB	Junction-to-board thermal resistance	48	53.4	34.8	50.1	°C/W
ψ_JT	Junction-to-top characterization parameter	18.6	16.5	26.9	16.7	°C/W
ψ_JB	Junction-to-board characterization parameter	47.8	52.9	34.7	49.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) The package thermal impedance is calculated in accordance with JESD 51-7.

6.5 Electrical Characteristics: SNx400

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_IK	V_CC = MIN and I_I = –12 mA				–1.5	V
V_OH	V_CC = MIN, V_IL = 0.8 V, and I_OH = –0.4 mA		2.4	3.4		V
V_OL	V_CC = MIN, V_IH = 2 V, and I_OL = 16 mA			0.2	0.4	V
I_I	V_CC = MAX and V_I = 5.5 V				1	mA
I_IH	V_CC = MAX and V_I = 2.4 V				40	µA
I_IL	V_CC = MAX and V_I = 0.4 V				–1.6	mA
I_OS	V_CC = MAX	SN5400	–20		–55	mA
I_OS	V_CC = MAX	SN7400	–18		–55	mA
I_CCH	V_CC = MAX and V_I = 0 V			4	8	mA
I_CCL	V_CC = MAX and V_I = 4.5 V			12	22	mA

6.6 Electrical Characteristics: SNx4LS00

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_IK	V_CC = MIN and I_I = –18 mA				–1.5	V
V_OH	V_CC = MIN, V_IL = MAX, and I_OH = –0.4 mA		2.5	3.4		V
V_OL	V_CC = MIN and V_IH = 2 V	I_OL = 4 mA		0.25	0.4	V
V_OL	V_CC = MIN and V_IH = 2 V	I_OL = 8 mA (SN74LS00)		0.35	0.5	V
I_I	V_CC = MAX and V_I = 7 V				0.1	mA
I_IH	V_CC = MAX and V_I = 2.7 V				20	µA
I_IL	V_CC = MAX and V_I = 0.4 V				–0.4	mA
I_OS	V_CC = MAX		–20		–100	mA
I_CCH	V_CC = MAX and V_I = 0 V			0.8	1.6	mA
I_CCL	V_CC = MAX and V_I = 4.5 V			2.4	4.4	mA

6.7 Electrical Characteristics: SNx4S00

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IK	V_CC = MIN and I_I = –18 mA			–1.2	V
V_OH	V_CC = MIN, V_IL = 0.8 V, and I_OH = –1 mA	2.5	3.4		V
V_OL	V_CC = MIN, V_IH = 2 V, and I_OL = 20 mA			0.5	V
I_I	V_CC = MAX and V_I = 5.5 V			1	mA
I_IH	V_CC = MAX and V_I = 2.7 V			50	µA
I_IL	V_CC = MAX and V_I = 0.5 V			–2	mA
I_OS	V_CC = MAX	–40		–100	mA
I_CCH	V_CC = MAX and V_I = 0 V		10	16	mA
I_CCL	V_CC = MAX and V_I = 4.5 V		20	36	mA

6.8 Switching Characteristics: SNx400

V_CC = 5 V, T_A = 25°C, and over operating free-air temperature range (unless otherwise noted). See Figure 2.

PARAMETER		FROM (INPUT)	TO (OUTPUT)	TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH		A or B	Y	R_L = 400 Ω and C_L = 15 pF		11	22	ns
t_PHL		A or B	Y	R_L = 400 Ω and C_L = 15 pF		7	15	ns

6.9 Switching Characteristics: SNx4LS00

V_CC = 5 V, T_A = 25°C, and over operating free-air temperature range (unless otherwise noted). See Figure 2.

PARAMETER		FROM (INPUT)	TO (OUTPUT)	TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH		A or B	Y	R_L = 2 kΩ and C_L = 15 pF		9	15	ns
t_PHL		A or B	Y	R_L = 2 kΩ and C_L = 15 pF		10	15	ns

6.10 Switching Characteristics: SNx4S00

V_CC = 5 V, T_A = 25°C, and over operating free-air temperature range (unless otherwise noted). See Figure 2.

PARAMETER	FROM (INPUT)	TO (OUTPUT)	TEST CONDITIONS	TYP	MAX	UNIT
t_PLH	A or B	Y	R_L = 280 Ω and C_L = 15 pF	3	4.5	ns
t_PLH	A or B	Y	R_L = 280 Ω and C_L = 50 pF	4.5
t_PHL	A or B	Y	R_L = 280 Ω and C_L = 15 pF	3	5
t_PHL	A or B	Y	R_L = 280 Ω and C_L = 50 pF	5

6.11 Typical Characteristics

C_L = 15 pF

SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00 D002_sdls025.gif

Figure 1. T_PHL (Across Devices)