SCES644D MARCH   2006  – December 2015 SN74AUP1G74

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, TA = 25°C
    6. 6.6  Electrical Characteristics, TA = -40°C to +85°C
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics, CL = 5 pF
    9. 6.9  Switching Characteristics, CL = 10 pF
    10. 6.10 Switching Characteristics, CL = 15 pF
    11. 6.11 Switching Characteristics, CL = 30 pF
    12. 6.12 Operating Characteristics
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information 
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Width)
    2. 7.2 Enable and Disable Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Power Button Circuit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DCU Package
8-Pin VSSOP
Top View
SN74AUP1G74 DCU_pinout_ces644.gif
RSE Package
8-Pin UQFN
Top View
SN74AUP1G74 RSE_pinout_ces644.gif
DQE Package
8-Pin X2SON
Top View
SN74AUP1G74 DQE_pinout_ces644.gif
YFP or YZP Package
8-Pin DSBGA
Top View
SN74AUP1G74 YFP_pinout_ces644.gif

Pin Functions(1)

PIN I/O DESCRIPTION
NAME VSSOP, X2SON UQFN DSBGA
CLK 1 7 A1 I Rising edge triggered clock signal input
CLR 6 2 C2 I Clear, Active low
D 2 6 B1 I Data input
GND 4 4 D1 — Ground
PRE 7 1 B2 I Preset, Active low
Q 5 3 D2 O Output
Q 3 5 C1 O Inverted output
VCC 8 8 A2 — Power supply