JAJST62 February   2024 SN74AVCH4T245-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCCA = 1.2V ± 0.12V
    7. 5.7  Switching Characteristics, VCCA = 1.5V ± 0.1V
    8. 5.8  Switching Characteristics, VCCA = 1.8V ± 0.15V
    9. 5.9  Switching Characteristics, VCCA = 2.5V ± 0.2V
    10. 5.10 Switching Characteristics, VCCA = 3.3V ± 0.3V
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Configurable Dual-Rail Design
      2. 7.3.2 Supports High Speed Translation
      3. 7.3.3 Ioff Supports Partial-Power-Down Mode Operation
      4. 7.3.4 Bus-Hold Circuitry
      5. 7.3.5 Vcc Isolation Feature
    4. 7.4 Device Functional Modes
  9.   Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

The SN74AVCH4T245-Q1 is a 4-bit, dual-supply noninverting bidirectional voltage level translation device. Ax pins and control pins (1DIR, 2DIR,1 OE, and 2 OE) are supported by VCCA, and Bx pins are supported by VCCB. The A port can accept I/O voltages ranging from 1.08V to 3.6V, while the B port can accept I/O voltages from 1.08V to 3.6V. A high on DIR allows data transmission from Ax to Bx and a low on DIR allows data transmission from Bx to Ax when OE is set to low. When OE is set to high, both Ax and Bx pins are in the high-impedance state. For more information, refer to the AVC Logic Family Technology and Applications application report.