JAJSGK7C
December 2018 – September 2020
SN74AXCH1T45
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Operating Characteristics: TA = 25°C
6.7
Typical Characteristics
7
Parameter Measurement Information
7.1
Load Circuit and Voltage Waveforms
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Standard CMOS Inputs
8.3.2
Balanced High-Drive CMOS Push-Pull Outputs
8.3.3
Partial Power Down (Ioff)
8.3.4
VCC Isolation
8.3.5
Over-voltage Tolerant Inputs
8.3.6
Negative Clamping Diodes
8.3.7
Fully Configurable Dual-Rail Design
8.3.8
Supports High-Speed Translation
8.3.9
Bus-Hold Data Inputs
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
Enable Times
9.2
Typical Applications
9.2.1
Interrupt Request Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curve
9.2.2
Universal Asynchronous Receiver-Transmitter (UART) Interface Application
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
静電気放電に関する注意事項
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DRY|6
MPDS221F
DCK|6
MPDS114E
DTQ|6
MUSS003A
DBV|6
MPDS026Q
サーマルパッド・メカニカル・データ
DRY|6
QFND138E
発注情報
jajsgk7c_oa
jajsgk7c_pm
12.6
Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.