JAJSFV6A August   2018  – January 2019 SN74AXCH8T245

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics, VCCA = 0.7 V
    7. 7.7  Switching Characteristics, VCCA = 0.8 V
    8. 7.8  Switching Characteristics, VCCA = 0.9 V
    9. 7.9  Switching Characteristics, VCCA = 1.2 V
    10. 7.10 Switching Characteristics, VCCA = 1.5 V
    11. 7.11 Switching Characteristics, VCCA = 1.8 V
    12. 7.12 Switching Characteristics, VCCA = 2.5 V
    13. 7.13 Switching Characteristics, VCCA = 3.3 V
    14. 7.14 Operating Characteristics: TA = 25°C
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Up-Translation and Down-Translation From 0.65 V to 3.6 V
      2. 9.3.2 Multiple Direction Control Pins
      3. 9.3.3 Bus-Hold Circuitry
      4. 9.3.4 Ioff Supports Partial-Power-Down Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Parameter Measurement Information

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f =1 MHz
  • Z0 = 50 Ω
  • dv / dt ≤ 1 ns/V

SN74AXCH8T245 SN74AXC8T245_LOAD_CIRCUIT.gif
1. CL includes probe and jig capacitance.
Figure 1. Load Circuit
SN74AXCH8T245 SN74AXC8T245_LOAD_CIRCUIT_CONDITIONS.gif
1. Output waveform on the conditions that input is driven to a valid Logic Low.
2. Output waveform on the condition that input is driven to a valid Logic High.
Figure 2. Load Circuit Conditions
SN74AXCH8T245 SN74AXC8T245_PROPAGATION_DELAY.gif
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 3. Propagation Delay
SN74AXCH8T245 SN74AXC8T245_ENABLE_TIME_AND_DISABLE_TIME.gif
1. Output waveform on the condition that input is driven to a valid Logic Low.
2. Output waveform on the condition that input is driven to a valid Logic High.
3. VCCO is the supply pin associated with the output port.
4. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 4. Enable Time And Disable Time