SN74GTL2014 4-Channel LVTTL to GTL Transceiver
- SCLS746A February 2014 – October 2014 SN74GTL2014
  
  PRODUCTION DATA.

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DATA SHEET

SN74GTL2014 4-Channel LVTTL to GTL Transceiver

1 Features

Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator
The LVTTL Inputs are Tolerant up to 5.5 V Allowing Direct Access to TTL or 5 V CMOS
The GTL Input/Output Operate up to 3.6 V, Allowing the Device to be Used in High Voltage Open-Drain Applications
VREF Goes Down to 0.5 V for Low Voltage CPU Usage
Partial Power-Down Permitted
Latch-up Protection Exceed 500 mA per JESD78
Package Option: TSSOP14
–40°C to 85°C Operating Temperature Range
ESD Protection on All Terminals
- 2000 V HBM, JESD22-A114
- 1000 V CDM, IEC61000-4-2

2 Applications

Server
Base Station
Wireline Communication

3 Description

The SN74GTL2014 is a 4-channel translator to interface between 3.3-V LVTTL chip set I/O and Xeon processor GTL–/GTL/GTL+ I/O.

The SN74GTL2014 integrates ESD protection cells on all terminals and is available in a TSSOP package (5.0 mm × 4.4 mm). The device is characterized over the free air temperature range of –40°C to 85°C.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SN74GTL2014	TSSOP (14)	5.00 mm × 4.40 mm

For all available packages, see the orderable addendum at the end of the data sheet.

4 Revision History

Changes from * Revision (February 2014) to A Revision

Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
Updated Specifications sectionGo
Updated LVTTL/TTL to GTL–/GTL/GTL+ application schematic. Go
Updated LVTTL/TTL to GTL–/GTL/GTL+ application schematic. Go
Added Power Supply Recommendations Go

5 Pin Configuration and Functions

TSSOP Package (14 Pin)

(Top View)

Pin Functions

PIN		DESCRIPTION
NAME	NUMBER	DESCRIPTION
A0	13	LVTTL data input/output
A01	12
A02	10
A03	9
B0	2	GTL data input/output
B01	3
B02	5
B03	6
DIR	1	Direction control input (LVTTL)
GND	7	Ground
	8
	11
VCC	14	Supply voltage
VREF	4	GTL reference voltage

6 Specifications

6.1 Absolute Maximum Ratings

Specified at T_A = –40°C to 85°C unless otherwise noted⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage		–0.5	4.6	V
I_IK	Input clamping current, VI < 0 V			–50	mA
V_SEL	Input control voltages SEL⁽²⁾⁽³⁾		–0.5	6	V
V_I	Input voltage	A port	–0.5	7	V
V_I	Input voltage	B port	–0.5	4.6	V
I_OK	Control input clamp current, V_O < 0 V			–50	mA
V_O	Output voltage	A port	–0.5	7	V
V_O	Output voltage	B port	–0.5	4.6	V
I_OL	Current into any output in the low state	A port		40	mA
I_OL	Current into any output in the low state	B port		80	mA
I_OH	Current into any output in the high state			–40	mA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to ground, unless otherwise specified

(3) V_I and V_O are used to denote specific conditions for V_I/O

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–55	150	°C
V_ESD⁽¹⁾	Human Body Model (HBM), JEDEC: JESD22-A114⁽²⁾	All pins	0	2	kV
V_ESD⁽¹⁾	IEC61000-4-2 contact discharge⁽³⁾	All pins	0	1	kV

(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage		3	3.3	3.6	V
V_TT	Termination voltage	GTL–	0.85	0.9	0.95	V
		GTL	1.14	1.2	1.26
		GTL+	1.35	1.5	1.65
V_REF	Reference voltage	Overall	0.5	2 / 3 V_TT	V_CC / 2	V
		GTL–	0.5	0.6	0.63
		GTL	0.76	0.8	0.84
		GTL+	0.87	1	1.1
V_I	Input voltage	A port	0	3.3	5.5⁽²⁾	V
V_I	Input voltage	B port	0	V_TT	3.6	V
V_IH	High-level input voltage	A port and DIR	2			V
V_IH	High-level input voltage	B port	V_REF + 50 mV			V
V_IL	Low-level input voltage	A port and DIR			0.8	V
V_IL	Low-level input voltage	B port			V_REF – 50 mV	V
I_OH	High-level input current	A port			–20	mA
I_OL	Low-level output current	A port			20	mA
I_OL	Low-level output current	B port			50	mA

(1) All unused control inputs of the device must be held at V_CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(2) The V_I(max) of LVTTL port is 3.6 V if configured as output (DIR=L)

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN74GTL2014	UNIT
		PW
		14 PINS
R_θJA	Junction-to-ambient thermal resistance	136.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	63.0
R_θJB	Junction-to-board thermal resistance	78.6
ψ_JT	Junction-to-top characterization parameter	11.9
ψ_JB	Junction-to-board characterization parameter	77.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Specified at T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	–40°C TO 85°C			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	A port	V_CC = 3 to 3.6 V, I_OH = –100 µA	V_CC – 0.2			V
V_OH	A port	V_CC = 3 V, I_OH = –16 mA	2			V
V_OL	A port	V_CC = 3 V, I_OL = 8 mA		0.28	0.4	V
	A port	V_CC = 3 V, I_OL = 16 mA		0.55	0.8
	B port	V_CC = 3 V, I_OL = 40 mA		0.23	0.4
I_I	A port	V_CC = 3.6 V, V_I = V_CC			±1	µA
		V_CC = 3.6, V_I = 0 V			±1
		V_CC = 3.6, V_I = 5.5 V			5
	B port	V_CC = 3.6 V, V_I= V_TT or GND			±1	µA
	Control pin	V_CC = 3.6 V, V_I = V_CC or 0 V			±1	µA
I_off	OFF-state output current on A port	V_CC = 0 V, V_IO = 0 to 3.6 V			±10	µA
	OFF-state output current on A port	V_CC = 0 V, V_IO 3.6 to 5.5V			±100
	OFF-state output current on B port	V_CC = 0 V, V_IO = 0 to 3.6 V			±10
I_CC	A port	V_CC = 3.6 V, V_I = V_CC or GND, I_O = 0		3	10	mA
I_CC	B port	V_CC = 3.6 V, V_I = V_TT or GND, I_O = 0		3	10	mA
∆I_CC	A port or control input	V_CC = 3.6 V, V_I = V_CC – 0.6 V			500	µA
C_I	Input capacitance of control pin	V_I = 3.0 V or 0 V		2	2.5	pF
C_IO	A port	V_O = 3 V or 0		4	6	pF
C_IO	B port	V_O= V_TT or 0		5.46	5.55	pF

6.6 Dynamic Electrical Characteristics

over operating range, T_A = –40°C to 85°C, V_CC = 1.65 to 4.6 V, GND = 0 V for GTL (see Functional Block Diagram)

PARAMETER		GTL−			GTL			GTL+			UNIT
		V_CC = 3.3 V ± 0.3 V V_REF = 0.6 V V_TT = 0.9 V			V_CC = 3.3 V ± 0.3 V V_REF = 0.8 V V_TT = 1.2 V			V_CC = 3.3 V ± 0.3 V V_REF = 1 V V_TT = 1.5 V
		MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
t_PLH (low to high propagation delay)	An to Bn		2.8	5		2.8	5		2.8	5	ns
t_PHL(high to low propagation delay)	An to Bn		3.3	7		3.4	7		3.4	7	ns
t_PLH (low to high propagation delay)	Bn to An		5.3	8		5.2	8		5.1	8	ns
t_PHL (high to low propagation delay)	Bn to An		5.2	8		4.9	7.16		4.7	7.16	ns

6.7 Typical Characteristics

Figure 1. GTL Vth+ and Vth– vs VREF (25°C)

Figure 3. GTL Vth+ and Vth– vs VREF (125°C)

Figure 2. GTL Vth+ and Vth– vs VREF (–40°C)