SCLS746A February   2014  – October 2014 SN74GTL2014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 5 V tolerance on LVTTL input
      2. 8.3.2 3.6 V tolerance on GTL Input/Output
      3. 8.3.3 Ultra-Low VREF and High Bandwidth
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 GTL-/GTL/GTL+ to LVTTL
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 LVTTL/TTL to GTL-/GTL/GTL+
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Detailed Description

8.1 Overview

The GTL2014 is a 4-channel translating transceiver designed for 3.3-V LVTTL system interface with a GTL–/GTL/GTL+ bus, where GTL–/GTL/GTL+ refers to the reference voltage of the GTL bus and the input/output voltage thresholds associated with it.

The direction pin allows the part to function as either a GTL-to-LVTTL sampling receiver or as a LVTTL-to-GTL interface.

8.2 Functional Block Diagram

fbd_cls746.gif

8.3 Feature Description

8.3.1 5 V tolerance on LVTTL input

The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V and allows direct access to TTL or 5 V CMOS inputs. The LVTTL outputs are not 5.5 V tolerant.

8.3.2 3.6 V tolerance on GTL Input/Output

The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used in higher voltage open-drain output applications.

8.3.3 Ultra-Low VREF and High Bandwidth

GTL2014’s VREF tracks down to 0.5 V for low voltage CPUs with excellent propagation delay performance. This feature allows the GTL2014 to support high data rates with the GTL– bus.

8.4 Device Functional Modes

The GTL2014 performs translation in two directions. One direction is GTL–/GTL/GTL+ to LVTTL when DIR is tied to GND. With appropriate VREF set up, the GTL input can be compliant with GTL–/GTL/GTL+. Another direction is LVTTL to GTL–/GTL/GTL+ when DIR is tied to VCC. 3.6 V tolerance on the GTL output allows the GTL outputs to pull up to any voltage level under 3.6 V.