JAJSQQ0F september   2000  – july 2023 SN74LV21A

PRODMIX  

  1.   1
  2. 1特長
  3. 2概要
  4. 3Revision History
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    7. 5.7  Switching Characteristics, VCC = 3.3 V ± 0.3 V
    8. 5.8  Switching Characteristics, VCC = 5 V ± 0.5 V
    9. 5.9  Noise Characteristics
    10. 5.10 Operating Characteristics
  7. 6Parameter Measurement Information
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|14
  • PW|14
  • DGV|14
  • DB|14
  • NS|14
サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The SN74LV21A devices perform the Boolean function Y = A • B • C • D in positive logic. These dual 4-input positive-AND gates are designed for 2-V to 5.5-V VCC operation.