SCES656E February   2006  – November 2016 SN74LV4046A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The most common use for the digital phased-locked loop (PLL) device is to match the VCO output to the same phase as the incoming signal and produce an error signal (DEMOUT) that indicates the amount of phase shift required for the match. This can be used as part of many complex systems.

8.2 Typical Application

SN74LV4046A sces656_app1.gif Figure 9. SN74LV4046A Digital Clock Signal Phase Comparison Application

8.2.1 Design Requirements

Table 1 and Table 2 lists the design requirements of the SN74LV4046A.

Table 1. Component Selection Criteria(1)

COMPONENT VALUE
R1 3 kΩ to 50 kΩ
R2 3 kΩ to 50 kΩ
R1 || R2 > 2.7 kΩ
C1 > 40 pF
R3 1 kΩ
C2 1 uF
R5 50 kΩ to 300 kΩ

Table 2. CPD(1)

CHIP SECTION CPD UNIT
Comparator 1 120 pF
VCO 120
(1) R1 between 3 kΩ and 50 kΩ
R2 between 3 kΩ and 50 kΩ
R1 + R2 parallel value > 2.7 kΩ
C1 > 40 pF

8.2.2 Detailed Design Procedure

  1. Recommended Input Conditions:
  2. Recommended Output Conditions:
  3. Frequency Selection Criterion:

8.2.3 Application Curves

Table 3 lists the application curves in the Typical Characteristics section.

Table 3. Table of Graphs

GRAPH TITLE FIGURE
Average Output Voltage vs Input Phase Difference Figure 6
Average Output Voltage vs Input Phase Difference Figure 7
Average Output Voltage vs Input Phase Difference Figure 8