SCES538G January   2004  – February 2020 SN74LVC1G38

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Logic Diagram (Positive Logic)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, CL = 15 pF
    7. 6.7  Switching Characteristics, CL = 30 pF or 50 pF, –40°C to +85°C
    8. 6.8  Switching Characteristics, CL = 30 pF or 50 pF, –40°C to +125°C
    9. 6.9  Operating Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1.     (Open Drain)
    2.     (Open Drain)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High-Drive Open-Drain Output
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-Voltage Tolerant Inputs
      6. 8.3.6 Up Translation and Down Translation Capable Outputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DPW|5
  • DBV|5
  • DSF|6
  • DCK|5
  • DRY|6
サーマルパッド・メカニカル・データ
発注情報

3 Description

The SN74LVC1G38 device is designed for 1.65-V to 5.5-V VCC operation.

This device is a single two-input NAND buffer gate with open-drain output. It performs the Boolean function Y = A × B or Y = A + B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Device Information(1)

DEVICE NAME PACKAGE BODY SIZE (NOM)
SN74LVC1G38DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74LVC1G38DCK SC70 (5) 2.00 mm × 1.25 mm
SN74LVC1G38DRY SON (6) 1.45 mm × 1.00 mm
SN74LVC1G38DSF SON (6) 1.00 mm × 1.00 mm
SN74LVC1G38YZP DSBGA (5) 0.89 mm × 1.39 mm
SN74LVC1G38DPW X2SON (5) 0.80 mm × 0.80 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN74LVC1G38 ld_ces538.gif