SCES902 September   2019 SN74LVC2GU04-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Logic Diagram (Positive Logic)
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristic
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1.      Logic Diagram (Positive Logic)
    3. 8.3 Feature Description
      1. 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Negative Clamping Diodes
      4. 8.3.4 Over-voltage Tolerant Inputs
      5. 8.3.5 Unbuffered Logic
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Thermal Information

THERMAL METRIC(1) DRY UNIT
(6 PINS)
RθJA Junction-to-ambient thermal resistance 233.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 144.6 °C/W
RθJB Junction-to-board thermal resistance 119.9 °C/W
ψJT Junction-to-top characterization parameter 15.8 °C/W
ψJB Junction-to-board characterization parameter 119.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report.