JAJSJD5E
October 1998 – July 2020
SN74LVCH32373A
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Operating Characteristics
6.9
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Standard CMOS Inputs
7.3.2
Balanced High-Drive CMOS Push-Pull Outputs
7.3.3
Partial Power Down (Ioff)
7.3.4
Over-voltage Tolerant Inputs
7.3.5
Clamp Diode Structure
7.3.6
Bus-Hold Data Inputs
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Power Considerations
8.2.1.2
Input Considerations
8.2.1.3
Output Considerations
8.2.1.4
Timing Considerations
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
サポート・リソース
11.3
Trademarks
11.4
静電気放電に関する注意事項
11.5
用語集
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
NMJ|96
サーマルパッド・メカニカル・データ
発注情報
jajsjd5e_oa
jajsjd5e_pm
8.2.1
Design Requirements
All signals in the system operate at the same voltage within the recommended operating range of the device
Inputs can be disconnected or placed into the high-impedance state; bus-hold circuitry will maintain the last known state at the input
Outputs must remain active at all times to prevent the bus from floating