JAJSJD5E October   1998  – July 2020 SN74LVCH32373A

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     6
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Standard CMOS Inputs
      2. 7.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 7.3.3 Partial Power Down (Ioff)
      4. 7.3.4 Over-voltage Tolerant Inputs
      5. 7.3.5 Clamp Diode Structure
      6. 7.3.6 Bus-Hold Data Inputs
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
        4. 8.2.1.4 Timing Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • NMJ|96
サーマルパッド・メカニカル・データ
発注情報

Pin Functions
PIN I/O DESCRIPTION
NAME NO.
1Q2 A1 Output Bank 1, Channel 2, Q Output
1Q4 B1 Output Bank 1, Channel 4, Q Output
1Q6 C1 Output Bank 1, Channel 6, Q Output
1Q8 D1 Output Bank 1, Channel 8, Q Output
2Q2 E1 Output Bank 2, Channel 2, Q Output
2Q4 F1 Output Bank 2, Channel 4, Q Output
2Q6 G1 Output Bank 2, Channel 6, Q Output
2Q7 H1 Output Bank 2, Channel 8, Q Output
3Q2 J1 Output Bank 3, Channel 2, Q Output
3Q4 K1 Output Bank 3, Channel 4, Q Output
3Q6 L1 Output Bank 3, Channel 6, Q Output
3Q8 M1 Output Bank 3, Channel 8, Q Output
4Q2 N1 Output Bank 4, Channel 2, Q Output
4Q4 P1 Output Bank 4, Channel 4, Q Output
4Q6 R1 Output Bank 4, Channel 6, Q Output
4Q7 T1 Output Bank 4, Channel 8, Q Output
1Q1 A2 Output Bank 1, Channel 1, Q Output
1Q3 B2 Output Bank 1, Channel 3, Q Output
1Q5 C2 Output Bank 1, Channel 5, Q Output
1Q7 D2 Output Bank 1, Channel 7, Q Output
2Q1 E2 Output Bank 2, Channel 1, Q Output
2Q3 F2 Output Bank 2, Channel 3, Q Output
2Q5 G2 Output Bank 2, Channel 5, Q Output
2Q8 H2 Output Bank 2, Channel 7, Q Output
3Q1 J2 Output Bank 3, Channel 1, Q Output
3Q3 K2 Output Bank 3, Channel 3, Q Output
3Q5 L2 Output Bank 3, Channel 5, Q Output
3Q7 M2 Output Bank 3, Channel 7, Q Output
4Q1 N2 Output Bank 4, Channel 1, Q Output
4Q3 P2 Output Bank 4, Channel 3, Q Output
4Q5 R2 Output Bank 4, Channel 5, Q Output
4Q8 T2 Output Bank 4, Channel 7, Q Output
1 OE A3 Input Bank 1, Output Enable, Active Low
GND B3 — Ground
VCC C3 — Positive Supply
GND D3 — Ground
GND E3 — Ground
VCC F3 — Positive Supply
GND G3 — Ground
2 OE H3 Input Bank 2, Output Enable, Active Low
3 OE J3 Input Bank 3, Output Enable, Active Low
GND K3 — Ground
VCC L3 — Positive Supply
GND M3 — Ground
GND N3 — Ground
VCC P3 Input Positive Supply
GND R3 — Ground
4 OE T3 Input Bank 4, Output Enable, Active Low
1LE A4 Input Bank 1, Latch Enable, Active Low
GND B4 — Ground
VCC C4 — Positive Supply
GND D4 — Ground
GND E4 — Ground
VCC F4 — Positive Supply
GND G4 — Ground
2LE H4 Input Bank 2, Latch Enable, Active Low
3LE J4 Input Bank 3, Latch Enable, Active Low
GND K4 — Ground
VCC L4 — Positive Supply
GND M4 — Ground
GND N4 — Ground
VCC P4 — Positive Supply
GND R4 — Ground
4LE T4 Input Bank 4, Latch Enable, Active Low
1D1 A5 Input Bank 1, Channel 1, Data Input
1D3 B5 Input Bank 1, Channel 3, Data Input
1D5 C5 Input Bank 1, Channel 5, Data Input
1D7 D5 Input Bank 1, Channel 7, Data Input
2D1 E5 Input Bank 2, Channel 1, Data Input
2D3 F5 Input Bank 2, Channel 3, Data Input
2D5 G5 Input Bank 2, Channel 5, Data Input
2D8 H5 Input Bank 2, Channel 8, Data Input
3D1 J5 Input Bank 3, Channel 1, Data Input
3D3 K5 Input Bank 3, Channel 3, Data Input
3D5 L5 Input Bank 3, Channel 5, Data Input
3D7 M5 Input Bank 3, Channel 7, Data Input
4D1 N5 Input Bank 4, Channel 1, Data Input
4D3 P5 Input Bank 4, Channel 3, Data Input
4D5 R5 Input Bank 4, Channel 5, Data Input
4D8 T5 Input Bank 4, Channel 8, Data Input
1D2 A6 Input Bank 1, Channel 2, Data Input
1D4 B6 Input Bank 1, Channel 4, Data Input
1D6 C6 Input Bank 1, Channel 6, Data Input
1D8 D6 Input Bank 1, Channel 8, Data Input
2D2 E6 Input Bank 2, Channel 2, Data Input
2D4 F6 Input Bank 2, Channel 4, Data Input
2D6 G6 Input Bank 2, Channel 6, Data Input
2D7 H6 Input Bank 2, Channel 7, Data Input
3D2 J6 Input Bank 3, Channel 2, Data Input
3D4 K6 Input Bank 3, Channel 4, Data Input
3D6 L6 Input Bank 3, Channel 6, Data Input
3D8 M6 Input Bank 3, Channel 8, Data Input
4D2 N6 Input Bank 4, Channel 2, Data Input
4D4 P6 Input Bank 4, Channel 4, Data Input
4D6 R6 Input Bank 4, Channel 6, Data Input
4D7 T6 Input Bank 4, Channel 7, Data Input