JAJSUB8 データシート

JAJSUB8D October 2000 – April 2024 SN65LBC172A , SN75LBC172A

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

DW|16
N|16
DW|20

サーマルパッド・メカニカル・データ

DW|20
- QFND313D
DW|16
- QFND313D

発注情報

5.7 Switching Characteristics

over recommended operating conditions

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH	Propagation delay time, low-to-high level output	R_L = 54Ω, C_L = 50pF, see Figure 6-4	5.5	8	11	ns
t_PHL	Propagation delay time, high-to-low level output		5.5	8	11	ns
t_r	Differential output voltage rise time		2	7.5	11	ns
t_f	Differential output voltage fall time		2	7.5	11	ns
t_sk(p)	Pulse skew \|t_PLH – t_PHL\|			0.6	2	ns
t_sk(o)	Output skew⁽¹⁾				2	ns
t_sk(pp)	Part-to-part skew⁽²⁾				3	ns
t_PZH	Propagation delay time, high-impedance-to-high-level output	See Figure 6-5			25	ns
t_PHZ	Propagation delay time, high-level-output-to-high impedance	See Figure 6-5			25	ns
t_PZL	Propagation delay time, high-impedance-to-low-level output	See Figure 6-6			30	ns
t_PLZ	Propagation delay time, low-level-output-to-high impedance	See Figure 6-6			20	ns

(1) Output skew (t_sk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.

(2) Part-to-part skew (t_sk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test circuits.