JAJSV24J October   1996  – July 2024 SN65LBC184 , SN75LBC184

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Driver
    6. 5.6  Electrical Characteristics: Receiver
    7. 5.7  Driver Switching Characteristics
    8. 5.8  Receiver Switching Characteristics
    9. 5.9  Dissipation Ratings
    10. 5.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SN65LBC184 Test Description
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

Because ESD transients have a wide frequency bandwidth from approximately 3MHz to 3GHz, high-frequency layout techniques must be applied during PCB design.

  • Use VCC and ground planes to provide low inductance. High frequency currents follow the path of least inductance and not the path of least impedance.
  • Apply 100nF to 220nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, or controller ICs on the board.
  • Use at least two vias for VCC and ground connections of bypass capacitors to minimize effective via-inductance.
  • Use 1kΩ to 10kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during transient events.