1 Features

• 4:28 Data Channel Expansion at up to
  1904 Mbps Throughput
• Suited for SVGA, XGA, or SXGA Display
  Data Transmission From Controller to
  Display With Very Low EMI
• Four Data Channels and Clock Low-Voltage
  Differential Channels In and 28 Data and
  Clock Low-Voltage TTL Channels Out
• Operates From a Single 3.3-V Supply With
  250 mW (Typical)
• 5-V Tolerant SHTDN Input
• Falling Clock-Edge-Triggered Outputs
• Packaged in Thin Shrink Small-Outline
  Package (TSSOP) With 20-Mil Terminal Pitch
• Consumes Less Than 1 mW When Disabled
• Pixel Clock Frequency Range of 31 MHz to
  68 MHz
• No External Components Required for PLL
• Inputs Meet or Exceed the Requirements of
  ANSI EIA/TIA-644 Standard

2 Applications

• Printers
• Appliances With an LCD
• Digital Cameras
• Laptop and PC Displays Industrial PC, Laptop, and other Factory Automation Displays Patient Monitor and Medical Equipment Displays Projectors Weight Scales

3 Description

The SN75LVDS82 FlatLink™ receiver contains four serial-in, 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit.

These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS83B, over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 for 21-bit transfers.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×) the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).

The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Spacer

Spacer