JAJSKZ3B December   2021  – December 2023 SN75LVPE5421

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Five-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
      4. 6.3.4 Receiver Detect State Machine
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Active Buffer Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe x8 Lane Switching
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RUA|42
サーマルパッド・メカニカル・データ
発注情報

5.5 DC Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
PACT Device active power  All channels enabled (PD = L) 720 970 mW
PSTBY Device power consumption in standby power mode All channels disabled (PD = H) 23 36 mW
Control IO
VIH High level input voltage SDA, SCL, PD, SEL pins 2.1 V
VIL Low level input voltage SDA, SCL, PD, SEL pins 1.08 V
VOH High level output voltage Rpull-up = 4.7kΩ (SDA, SCL pins) 2.1 V
VOL Low level output voltage IOL = –4mA (SDA, SCL pins) 0.4 V
IIH,SEL Input high leakage current for SEL pins VInput =  VCC, for SEL pin 100 µA
IIH Input high leakage current VInput = VCC, (SCL, SDA, PD pins) 10 µA
IIL Input low leakage current VInput = 0V, (SCL, SDA, PD, SEL pins) -10 µA
IIH,FS Input high leakage current for fail safe input pins VInput = 3.6V, VCC = 0V, (SCL, SDA, PD, SEL pins) 200 µA
CIN-CTRL Input capacitance SCL, SDA, PD, SEL pins 1.6 pF
5 Level IOs (MODE, GAIN, EQ1, EQ0, RX_DET pins)
IIH_5L Input high leakage current, 5 level IOs VIN = 2.5V 10 µA
IIL_5L Input low leakage current for all 5 level IOs except MODE. VIN = GND -10 µA
IIL_5L,MODE Input low leakage current for MODE pin VIN = GND -200 µA
Receiver
VRX-DC-CM RX DC common mode voltage Device is in active or standby state 1.4 V
ZRX-DC Rx DC single-ended impedance 50 Ω
ZRX-HIGH-IMP-DC-POS DC input CM input impedance during Reset or power-down Inputs are at VRX-DC-CM voltage 20 kΩ
Transmitter
ZTX-DIFF-DC DC differential Tx impedance Impedance of Tx during active signaling, VID,diff = 1Vpp 100 Ω
VTX-DC-CM Tx DC common mode Voltage 1.0 V
ITX-SHORT Tx short circuit current Total current the Tx can supply when shorted to GND 70 mA