JAJSCH4 September   2016 SN75LVPE801

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  SATA Express
      2. 9.3.2  Receiver Termination
      3. 9.3.3  Receiver Internal Bias
      4. 9.3.4  Receiver Equalization
      5. 9.3.5  OOB/Squelch
      6. 9.3.6  Auto Low Power
      7. 9.3.7  Transmitter Output Signal
      8. 9.3.8  Transmitter Common Mode
      9. 9.3.9  De-Emphasis
      10. 9.3.10 Transmitter Termination
    4. 9.4 Device Functional Modes
      1. 9.4.1 Active
      2. 9.4.2 Squelch
      3. 9.4.3 Auto Low Power
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical SATA Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
      4. 10.2.4 SATA Express Applications
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
        3. 10.2.4.3 Application Curve
      5. 10.2.5 PCIe Applications
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Return Current and Plane References
      2. 12.1.2 Split Planes - What to Avoid
      3. 12.1.3 Avoiding Crosstalk
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC(2) –0.5 4 V
Voltage Differential I/O –0.5 4 V
Control I/O –0.5 VCC + 0.5
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground pin.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±6000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

typical values for all parameters are at VCC = 3.3 V and TA = 25°C; all temperature limits are specified by design
MIN TYP MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
Coupling capacitor 75 100 200 nF
TA Operating free-air temperature 0 85 °C

7.4 Thermal Information

THERMAL METRIC(1) SN75LVPE801 UNIT
DRF (WSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 97.8 °C/W
RθJCtop Junction-to-case (top) thermal resistance 81.9 °C/W
RθJB Junction-to-board thermal resistance 65.6 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 65.6 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 19.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE PARAMETERS
ICCMax-s Active mode supply current EQ/DE = NC, K28.5 pattern at 8 Gbps, VID = 700 mVpp 29 40 mA
ICCPS Auto power save mode ICC When auto low power conditions are met 3.3 5.9 mA
Maximum data rate 8 Gbps
OOB
VOOB Input OOB threshold F = 750 MHz 50 70 90 mVpp
DVdiffOOB OOB differential delta 25 mV
DVCMOOB OOB common-mode delta 50 mV
CONTROL LOGIC
VIH High-level input voltage For all control pins 1.4 V
VIL Low-level input voltage 0.5 V
VINHYS Input hysteresis 115 mV
IIH High-level input current VIH = VCC (DE/EQ) 20 μA
IIL Low-level input current VIL = 0V (DE/EQ) 10 μA
RECEIVER AC/DC
ZDIFFRX Differential input impedance 85 100 115 Ω
ZSERX Single-ended input impedance 40 Ω
VCMRX Common-mode voltage 1.7 V
RLDiffRX Differential mode return loss (RL) f = 150 MHz to 300 MHz 20 26 dB
f = 300 MHz to 600 MHz 18 22
f = 600 MHz to 1.2 GHz 14 17
f = 1.2 GHz to 2.4 GHz 10 12
f = 2.4 GHz to 3 GHz 8 12
f = 3 GHz to 5 GHz 6 11
RXDiffRLSlope Differential mode RL slope f = 300 MHz to 6 GHz (see Figure 6) –13 dB/dec
RLCMRX Common-mode return loss f = 150 MHz to 300 MHz 8 9 dB
f = 300 MHz to 600 MHz 14 17
f = 600 MHz to 1.2 GHz 12 18
f = 1.2 GHz to 2.4 GHz 8 10
f = 2.4 GHz to 3 GHz 6 8
f = 3 GHz to 5 GHz 6 8.5
VdiffRX Differential input voltage PP f = 1.5 GHz and 3 GHz 120 1600 mVpp
IBRX Impedance balance f = 150 MHz to 300 MHz 30 41 dB
f = 300 MHz to 600 MHz 34 41
f = 600 MHz to 1.2 GHz 24 33
f = 1.2 GHz to 2.4 GHz 14 24
f = 2.4 GHz to 3 GHz 12 26
f = 3 GHz to 5 GHz 6 18
f = 5 GHz to 6.5 GHz 5 18
TRANSMITTER AC/DC
ZdiffTX Pair differential impedance 85 100 122 Ω
ZSETX Single-ended input impedance 40 Ω
VTXtrans Sequencing transient voltage Transient voltages on the serial data bus during power sequencing (lab load) –1.2 0.3 1.2 V
RLDiffTX Differential mode return loss f = 150 MHz to 300 MHz 14 22 dB
f = 300 MHz to 600 MHz 12 21
f = 600 MHz to 1.2 GHz 11 18
f = 1.2 GHz to 2.4 GHz 10 14
f = 2.4 GHz to 3 GHz 10 14
f = 3 GHz to 5 GHz 8 14
TXDiffRLSlope Differential mode RL slope f = 300 MHz to 3 GHz (see Figure 6) –13 dB/dec
RLCMTX Common-mode return loss f = 150 MHz to 300 MHz 10 20 dB
f = 300 MHz to 600 MHz 9 16
f = 600 MHz to 1.2 GHz 8 13.5
f = 1.2 GHz to 2.4 GHz 6 8.5
f = 2.4 GHz to 3 GHz 5 8
f = 3 GHz to 5 GHz 4 7
IBTX Impedance balance f = 150 MHz to 300 MHz 34 38 dB
f = 300 MHz to 600 MHz 32 38
f = 600 MHz to 1.2 GHz 24 33
f = 1.2 GHz to 2.4 GHz 18 25
f = 2.4 GHz to 3 GHz 18 25
f = 3 GHz to 5 GHz 12 21
f = 5 GHz to 6.5 GHz 8 21
DiffVppTX Differential output voltage swing f = 3 GHz (under no interconnect loss) 400 650 900 mVpp
VCMAC_TX TX AC CM voltage At 1.5 GHz 15 50 mVpp
At 3 GHz 10 26 dBmV (rms)
At 6 GHz 12 30 dBmV (rms)
VCMTX Common-mode voltage 1.70 V
TRANSMITTER JITTER 3 Gbps
DJTX Residual deterministic jitter VID = 500 mVpp, UI = 333 ps, K28.5 control character, see Figure 7 0.12 0.19 UIpp
RJTX Random jitter VID = 500 mVpp, UI = 333 ps, K28.7 control character, see Figure 7 1 2 ps-rms
TRANSMITTER JITTER 6 Gbps
DJTX Residual deterministic jitter VID = 500 mVpp, UI = 167 ps, K28.5 control character, see Figure 7 0.12 0.34 UIpp
RJTX Random jitter VID = 500 mVpp, UI = 167 ps, K28.7 control character, see Figure 7 0.95 2 ps-rms
TRANSMITTER JITTER 8 Gbps
DJTX Residual deterministic jitter VID = 500 mVpp, UI = 125 ps, K28.5 control character, see Figure 7 4.7 5.76 8.7 (ps) (DD)
RJTX Random jitter VID = 500 mVpp, UI = 125 ps, K28.5 control character, see Figure 7 0.93 0.94 0.95 ps-rms
DJTX Residual deterministic jitter VID = 500 mVpp, UI = 125 ps, K28.7 control character, see Figure 7 0.8 1.24 2.7 (ps) (DD)
RJTX Random jitter VID = 500 mVpp, UI = 125 ps, K28.7 control character, see Figure 7 0.9 0.92 0.93 ps-rms

7.6 Timing Requirements

MIN TYP MAX UNIT
DEVICE PARAMETERS
tPDelay Propagation delay Measured using K28.5 pattern (see Figure 1) 275 350 ps
AutoLPENTRY Auto low power entry time Electrical idle at input (see Figure 3) 11 μs
AutoLPEXIT Auto low power exit time After first signal activity (see Figure 3) 33 50 ns
OOB
tOOB1 OOB mode enter See Figure 2 1 5 ns
tOOB2 OOB mode exit See Figure 2 1 5 ns
RECEIVER AC/DC
t20-80RX Rise and fall time Rise times and fall times measured between 20% and 80% of the signal. SATA 8 Gbps speed measured 1" from device pin. 62 75 ps
tskewRX Differential skew Difference between the single-ended mid-point of the RX+ signal rising and falling edge, and the single-ended mid-point of the RX– signal falling and rising edge. 30 ps
TRANSMITTER AC/DC
t20-80TX Rise and fall time Rise times and fall times measured between 20% and 80% of the signal. At 8 Gbps under no load conditions measured at the pin. 44 58 85 ps
tskewTX Differential skew Difference between the single-ended mid-point of the TX+ signal rising edge and falling edge, and the single-ended mid-point of the TX– signal falling edge and rising edge, D1, D0 = VCC 2 15 ps
txR/Flmb TX rise and fall imbalance At 8 Gbps 6% 20%
txAmplmb TX amplitude imbalance 1% 10%
TRANSMITTER JITTER
Rise and Fall time 46.5% 47.5% 48.3%
Rise and Fall mismatch 1.5% 3%
SN75LVPE801 delay_tim_lls912.gif Figure 1. Propagation Delay Timing Diagram
SN75LVPE801 exit_tim_lls912.gif Figure 2. OOB Enter and Exit Timing
SN75LVPE801 auto_low_pwr_llse63.gif Figure 3. Auto Low Power Mode Entry and Exit Timing

7.7 Typical Characteristics

SN75LVPE801 D001_SLLSEL6.gif
A function of input trace length of 4 mil FR-4
xx
Figure 4. Deterministic Jitter vs Data Rate
SN75LVPE801 D002_SLLSEL6.gif
Function of data rate after equalizing for 32" of input
FR = 4 trace, EQ = 1, DE = 1
Figure 5. Deterministic Jitter vs Launch Amplitude