This section describes the necessary steps to configure the TAA3020 for this specific application. The following steps provide a sequence of items that must be executed in the time between powering the device up and reading data from the device or transitioning from one mode to another mode of operation.

1. Apply power to the device:
   1. Power-up the IOVDD and AVDD power supplies
   2. Wait for at least 1 ms to allow the device to initialize the internal registers initialization
   3. The device now goes into sleep mode (low-power mode < 10 µA)
2. Transition from sleep mode to active mode whenever required for the recording operation:
   1. Wake up the device by writing to P0_R2 to disable sleep mode
   2. Wait for at least 1 ms to allow the device to complete the internal wake-up sequence
   3. Override default configuration registers or programmable coefficients value as required (this step is optional)
   4. Enable all desired input channels by writing to P0_R115
   5. Enable all desired audio serial interface output channels by writing to P0_R116
   6. Power-up the ADC, MICBIAS, and PLL by writing to P0_R117
   7. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio

      This specific step can be done at any point in the sequence after step a.

      See the Phase-Locked Loop (PLL) and Clock Generation section for supported sample rates and the BCLK to FSYNC ratio.

   8. The device recording data are now sent to the host processor via the TDM audio serial data bus
3. Transition from active mode to sleep mode (again) as required in the system for low-power operation:
   1. Enter sleep mode by writing to P0_R2 to enable sleep mode
   2. Wait at least 6 ms (when FSYNC = 48 kHz) for the volume to ramp down and for all blocks to power down
   3. Read P0_R119 to check the device shutdown and sleep mode status
   4. If the device P0_R119_D7 status bit is 1'b1 then stop FSYNC and BCLK in the system
   5. The device now goes into sleep mode (low-power mode < 10 µA) and retains all register values
4. Transition from sleep mode to active mode (again) as required for the recording operation:
   1. Wake up the device by writing to P0_R2 to disable sleep mode
   2. Wait for at least 1 ms to allow the device to complete the internal wake-up sequence
   3. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
   4. The device recording data are now sent to the host processor via the TDM audio serial data bus
5. Repeat step 2 to step 4 as required for configuration changes or step 3 to step 4 for mode transitions