JAJSVL7 November   2024 TAA3020

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 5.9  Switching Characteristics: TDM, I2S or LJ Interface
    10. 5.10 Timing Requirements: PDM Digital Microphone Interface
    11. 5.11 Switching Characteristics: PDM Digial Microphone Interface
    12. 5.12 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configurations
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Programmable Microphone Bias
      6. 6.3.6  Signal-Chain Processing
        1. 6.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 6.3.6.2 Programmable Channel Gain Calibration
        3. 6.3.6.3 Programmable Channel Phase Calibration
        4. 6.3.6.4 Programmable Digital High-Pass Filter
        5. 6.3.6.5 Programmable Digital Biquad Filters
        6. 6.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 6.3.6.7 Configurable Digital Decimation Filters
          1. 6.3.6.7.1 Linear Phase Filters
            1. 6.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
            2. 6.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
            3. 6.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
            4. 6.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
            5. 6.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
            6. 6.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
            7. 6.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
            8. 6.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
            9. 6.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
          2. 6.3.6.7.2 Low-Latency Filters
            1. 6.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 6.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 6.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 6.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 6.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 6.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
          3. 6.3.6.7.3 Ultra-Low Latency Filters
            1. 6.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 6.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 6.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 6.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 6.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 6.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
            7. 6.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
      7. 6.3.7  Automatic Gain Controller (AGC)
      8. 6.3.8  Voice Activity Detection (VAD)
      9. 6.3.9  Digital PDM Microphone Record Channel
      10. 6.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
            1. 6.5.1.1.1.1 I2C Single-Byte and Multiple-Byte Transfers
              1. 6.5.1.1.1.1.1 I2C Single-Byte Write
              2. 6.5.1.1.1.1.2 I2C Multiple-Byte Write
              3. 6.5.1.1.1.1.3 I2C Single-Byte Read
              4. 6.5.1.1.1.1.4 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
    2. 7.2 Page_0 Registers
    3. 7.3 Page_1 Registers
    4. 7.4 Programmable Coefficient Registers
      1. 7.4.1 Programmable Coefficient Registers: Page 2
      2. 7.4.2 Programmable Coefficient Registers: Page 3
      3. 7.4.3 Programmable Coefficient Registers: Page 4
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Two-Channel Analog Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
      2. 8.2.2 Four-Channel Digital PDM Microphone Recording
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Example Device Register Configuration Script for EVM Setup
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.1 Overview

The TAA3020 is a high-performance, low-power, flexible, 2-channel, audio analog-to-digital converter (ADC) with extensive feature integration. This device is intended for applications in voice-activated systems, professional microphones, audio conferencing, portable computing, communication, and entertainment applications. The high dynamic range of the device enables far-field audio recording with high fidelity. This device integrates a host of features that reduces cost, board space, and power consumption in space-constrained, battery-powered, consumer, home, and industrial applications.

The TAA3020 consists of the following blocks:

  • 2-channel, multibit, high-performance delta-sigma (ΔΣ) ADC
  • Configurable single-ended or differential audio inputs
  • Low-noise, programmable microphone bias output
  • Automatic gain controller (AGC)
  • Programmable decimation filters with a linear-phase filter or a low-latency filter
  • Programmable channel gain, volume control, biquad filters for each channel
  • Programmable phase and gain calibration with fine resolution for each channel
  • Programmable high-pass filter (HPF), and digital channel mixer
  • Pulse density modulation (PDM) microphone 4-channel interface with a high-performance decimation filter
  • Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks
  • Integrated digital and analog voltage regulators to support single-supply operation

Communication to the TAA3020 for configuring the control registers is supported using an I2C interface. The device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I2S, or left-justified (LJ)] to transmit audio data seamlessly in the system across devices.

The TAA3020 can support multiple devices by sharing the common TDM bus across devices. Moreover, the device includes a daisy-chain feature as well. These features relax the shared TDM bus timing requirements and board design complexities when operating multiple devices for applications requiring high audio data bandwidth.

Table 6-1 lists the reference abbreviations used throughout this document to registers that control the device.

Table 6-1 Abbreviations for Register References
REFERENCE ABBREVIATION DESCRIPTION EXAMPLE
Page y, register z, bit k Py_Rz_Dk Single data bit. The value of a single bit in a register. Page 4, register 36, bit 0 = P4_R36_D0
Page y, register z, bits k-m Py_Rz_D[k:m] Range of data bits. A range of data bits (inclusive). Page 4, register 36, bits 3-0 = P4_R36_D[3:0]
Page y, register z Py_Rz One entire register. All eight bits in the register as a unit. Page 4, register 36 = P4_R36
Page y, registers z-n Py_Rz-Rn Range of registers. A range of registers in the same page. Page 4, registers 36, 37, 38 = P4_R36-R38