JAJSNO9 January   2022 TAA5212

ADVANCE INFORMATION  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Serial Interfaces
        1. 8.3.2.1 Control Serial Interfaces
        2. 8.3.2.2 Audio Serial Interfaces
          1. 8.3.2.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.2.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.2.2.3 Left-Justified (LJ) Interface
        3. 8.3.2.3 Using Multiple Devices With Shared Buses
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Programmable Microphone Bias
      7. 8.3.7 Signal-Chain Processing
        1. 8.3.7.1 ADC Signal-Chain
          1. 8.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 8.3.7.1.2 Programmable Channel Gain Calibration
          3. 8.3.7.1.3 Programmable Channel Phase Calibration
          4. 8.3.7.1.4 Programmable Digital High-Pass Filter
          5. 8.3.7.1.5 Programmable Digital Biquad Filters
          6. 8.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 8.3.7.1.7 Configurable Digital Decimation Filters
            1. 8.3.7.1.7.1 Linear Phase Filters
              1. 8.3.7.1.7.1.1 Sampling Rate: 16 kHz or 14.7 kHz
              2. 8.3.7.1.7.1.2 Sampling Rate: 24 kHz or 22.05 kHz
              3. 8.3.7.1.7.1.3 Sampling Rate: 32 kHz or 29.4 kHz
              4. 8.3.7.1.7.1.4 Sampling Rate: 48 kHz or 44.1 kHz
              5. 8.3.7.1.7.1.5 Sampling Rate: 96 kHz or 88.2 kHz
      8. 8.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 8.3.9 Programmable Channel Phase Calibration
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1 VEGA Registers
      2. 8.5.2 TAA5212 Registers
      3. 8.5.3 TAA5212 Registers
    6. 8.6 Feature Description
    7. 8.7 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報
Left-Justified (LJ) Interface

The standard LJ protocol is defined for only two channels: left and right. The device extends the same protocol timing for multichannel operation. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. Immediately after the right slot 0 data transmission, the remaining right slot data are transmitted in order. FSYNC is transmitted on the falling edge of BCLK. Figure 8-10 to Figure 8-13 illustrate the protocol timing for LJ operation with various configurations.

GUID-27FAEB63-E2CE-4467-892A-18A93E46761F-low.gifFigure 8-10 LJ Mode Standard Protocol Timing (TX_OFFSET = 0)
GUID-380DFCCD-14C2-46CC-9385-7393E94CA7D5-low.gifFigure 8-11 LJ Protocol Timing (TX_OFFSET = 2)
GUID-BA1D20ED-D5DC-4FC3-8950-B6DAC2ABC7DB-low.gifFigure 8-12 LJ Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
GUID-E23E32F9-CA07-4AC4-BDB0-4E8FE063AB0D-low.gifFigure 8-13 LJ Protocol Timing (TX_OFFSET = 1 and BCLK_POL = 1)

For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels (including left and right slots) times the programmed word length of the output channel data. The device FSYNC high pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC low pulse must be number of BCLK cycles wide that is greater than or equal to the number of active right slots times the data word length configured. For a higher BCLK frequency operation, using LJ mode with a TX_OFFSET value higher than 0 is recommended.