JAJSNO8A January   2022  – October 2024 TAA5242

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
        3. 6.3.2.3 Left-Justified (LJ) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Analog Input Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Integrated Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 Configurable Digital Decimation Filters
          1. 6.3.7.1.1 Linear-phase filters
            1. 6.3.7.1.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.7.1.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.7.1.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.7.1.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.7.1.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.7.1.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.7.1.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 6.3.7.1.2 Low-latency Filters
            1. 6.3.7.1.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 6.3.7.1.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 6.3.7.1.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 6.3.7.1.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 6.3.7.1.2.5 Sampling Rate: 192kHz or 176.4kHz
        2. 6.3.7.2 Programmable Digital High-Pass Filter
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Performance Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.3 Detailed Design Procedure

This section describes the necessary steps to configure the TAA5242 for this specific application.

  1. Audio Serial Interface (ASI) Mode is configured based on the MD0 pin setting which needs to be provided along with the power supplies. Configure MD0 to be to be either pulled up to AVDD or down to VSS with appropriate resistor values. MD0 is to be grounded for this application case.
  2. Apply power to the device:
    1. Power up the AVDD and IOVDD supplies.
    2. Ensure that MD0 pin setting is stable as soon as power supplies are up and wait for at least 2ms to allow the device to initialize for this mode of operation.
    3. The device is now in sleep mode (low power mode <1.5mA).
  3. Configure the Mode pins MD1 to MD6 as per the system requirements:
    1. Pull up to IOVDD or pull down to VSS on MD1 to MD6 pins as per the required configuration. The MD1 to MD6 pins are grounded for this application's use-case.
  4. Apply the ASI clocks (BCLK and FSYNC) to wake up the device.
  5. To put the device back in sleep mode, stop the clocks:
    1. Wait at least 100ms to allow the device to complete shutdown sequence.
    2. Change the device configurations by changing MD1 to MD6 pin settings as per requirement.

  6. To change the ASI mode, re-configure MD0 pin and power-cycle the device.

  7. Repeat steps 1-6 as required for mode transitions.