10 Power Supply Recommendations

The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, after all Mode pins are stable, then only initiate the clocks to initialize the device.

For the supply power-up requirement, t₁, t₂ and t₃ must be at least 2 ms to allow the device to initialize the internal registers. See the Section 8.4 section for details on how the device operates in various modes after the device power supplies are settled to the recommended operating voltage levels. For the supply power-down requirement, t₄, t₅ and t₆ must be at least 10 ms. This timing (as shown in Figure 10-1) allows the device to ramp down the volume on the record data, power down the analog and digital blocks, and put the device into low power mode.

Figure 10-1 Power-Supply Sequencing Requirement Timing Diagram

Make sure that the supply ramp rate is slower than 0.1V/µs and that the wait time between a power-down and a power-up event is at least 100 ms.

The TAD5242 supports a single AVDD supply operation by integrating an on-chip digital regulator, DREG, and an analog regulator, AREG.