JAJSNP1 December   2023 TAD5242

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Analog Output Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 DAC Signal-Chain
        1. 8.3.6.1 Configurable Digital Interpolation Filters
          1. 8.3.6.1.1 Linear Phase Filters
            1. 8.3.6.1.1.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.1.1.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.1.1.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.1.1.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.1.1.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.6.1.1.6 Sampling Rate: 384 kHz or 352.8 kHz
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
  11. 10Power Supply Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.2.1 Time Division Multiplexed Audio (TDM) Interface

In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK. Figure 8-2 and Figure 8-3 show the protocol timing for TDM operation with various configurations.

GUID-009F6C1F-44BF-483F-B769-16F7F1C9B789-low.gif Figure 8-2 TDM Mode Protocol Timing (MD0 shorted to ground with 4.7K Ohms) In Target Mode
GUID-A15BCAF9-FD3D-406D-832C-374D732BA196-low.gif Figure 8-3 TDM Mode Protocol Timing (MD0 shorted to AVDD with 4.7K Ohms) In Controller Mode

For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels times the 32-bits word length of the output channel data. The device transmits a zero data value on SDOUT for the extra unused bit clock cycles. The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well.