JAJSVG1 August   2024 TAS2120

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Boost
      5. 6.4.5 Supply Voltage Monitors
      6. 6.4.6 Thermal Protection
      7. 6.4.7 Clocks and PLL
        1. 6.4.7.1 Auto clock based wakeup and clock errors
      8. 6.4.8 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Mono/Stereo Configuration
        2. 7.2.2.2 Boost Converter Passive Devices
        3. 7.2.2.3 EMI Passive Devices
        4. 7.2.2.4 Miscellaneous Passive Devices
      3. 7.2.3 Application Performance Plots
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

TAS2120 QFN Package Bottom ViewFigure 4-1 QFN Package Bottom View
Pin Functions
PINType(1)DESCRIPTION
NAMENO.
BGND12PBoost ground. Connect to PCB GND plane strongly with multiple vias.
DREG26PDigital core voltage regulator output. Bypass to GND with a capacitor. Do not connect to an external load.
FSYNC8II2S word clock or TDM frame sync.
GREG17PHigh-side gate CP regulator output. Do not connect to an external load.
GND22, 23, 25PConnect to PCB GND plane. Strong connection to ground plane required through multiple vias.
IOVDD5P1.8V or 3.3V Digital IO supply. Decouple to GND with capacitor.
IRQZ6OOpen drain, active low interrupt pin. Pull up to IOVDD with resistor if optional internal pullup is not used.
OUT_N19OClass-D negative output.
OUT_P20OClass-D positive output.
PGND21PClass-D Power stage ground. Connect to PCB GND plane strongly through multiple vias.
PVDD18PIntegrated boost output and Class-D power stage supply.
SBCLK9II2S/TDM serial bit clock.
SDIN10II2S or TDM serial data input.
SDOUT11I/OI2S or TDM serial data output.
SDZ7IActive low hardware shutdown.
SEL116I

HW Mode: Select 1 Pin. Amplifier gain level selection with volume ramp enable and disable options.

I2C Mode: Short to GND for I2C mode selection.

SEL2_SCL4I

HW Mode: Select 2 Pin. I2S, TDM, Left justified selection.

I2C Mode: Clock Pin. Pull up to IOVDD with a resistor.

SEL3_SDA3I/O

HW Mode: Select 3 Pin. Data valid rising edge and falling edge selection.

I2C Mode: Data Pin. Pull up to IOVDD with a resistor.

SEL4_ADDR2I

HW Mode: Select 4 Pin.Y-bridge threshold configuration setting.

I2C Mode: I2C address pin.

SEL51I/O

HW Mode: Select5 Pin. Boost 1S, 2S, External PVDD mode selection.

SW13PBoost converter switch input.
VBAT15PBattery power supply input. Connect to a 2.5 to 5.5V supply and decouple with a capacitor.
VBAT_SNS14IBattery sense terminal. Connect to 1S or 2S battery supply for remote battery sensing. Ground the pin if remote sensing is not used.
VDD24PConnect to 1.8V supply and decouple to GND with capacitor.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.