JAJSVG0 September   2024 TAS2320

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Supply Voltage Monitors
      5. 6.4.5 Thermal Protection
      6. 6.4.6 Clocks and PLL
        1. 6.4.6.1 Auto clock based wakeup and clock errors
      7. 6.4.7 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Mono/Stereo Configuration
        2. 7.2.2.2 EMI Passive Devices
        3. 7.2.2.3 Miscellaneous Passive Devices
      3. 7.2.3 Application Performance Plots
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.2 Faults and Status

During power-up sequencing, the power-on-reset circuit (POR) monitors the VDD and IOVDD pins and holds device in reset (including all the configuration registers) until the supplies are valid. Any supply voltage dip on VDD or IOVDD below the UVLO voltage thresholds resets the device immediately along with all the register configurations.

During operation modes, the device monitors internal device status and fault conditions and can notify the host of error and status conditions using the IRQZ interrupt pin and internal I2C based interrupt registers. The interrupt generation in IRQZ pin can be masked by configuring the corresponding Interrupt mask register bit.
Table 6-10 lists the different faults and interrupts that the device monitors and the corresponding configuration bits to enable/disable the interrupt generation and reading the I2C interrupt status
Table 6-10 Faults and Interrupts
CategoryInterruptInterrupt Mask register bitDefault Mask statusInterrupt Latched status bit
Limiter & Brown out protection Section 6.4.2.4Brownout detectedINT_MASK0[3]Not MaskedINT_LTCH0[3]
BOP ActiveINT_MASK0[2]Not MaskedINT_LTCH0[2]
BOP infinite holdINT_MASK0[7]Not MaskedINT_LTCH0[7]
Limiter ActiveINT_MASK0[4]Not MaskedINT_LTCH0[4]
Limiter attenuationINT_MASK0[6]Not MaskedINT_LTCH0[6]
Supply below inflection pointINT_MASK0[5]Not MaskedINT_LTCH0[5]
Supply Voltage MonitorsSection 6.4.4PVDD Over voltageINT_MASK3[2]Not MaskedINT_LTCH3[2]
PVDD Under voltageINT_MASK1[7]Not MaskedINT_LTCH1[7]
VBAT2S supply under voltageINT_MASK1[6]Not MaskedINT_LTCH1[6]
VBAT supply under voltageINT_MASK4[7]Not MaskedINT_LTCH4[7]
Thermal protectionSection 6.4.5Thermal warning at 135CINT_MASK1[4]MaskedINT_LTCH1[4]
Thermal warning at 125CINT_MASK1[3]MaskedINT_LTCH1[3]
Thermal warning at 115CINT_MASK1[2]MaskedINT_LTCH1[2]
Thermal warning at 105CINT_MASK1[1]MaskedINT_LTCH1[1]
Over temperature errorINT_MASK3[7]Not MaskedINT_LTCH3[7]
Clock protectionSection 6.4.6.1Clock errorINT_MASK2[3]Not MaskedINT_LTCH2[3]
Pre-Power-up Clock errorINT_MASK4[2]Not MaskedINT_LTCH4[2]
Clock ratio change errorINT_MASK2[2]Not MaskedINT_LTCH2[2]
Fs change errorINT_MASK2[1]Not MaskedINT_LTCH2[1]
Fs invalid errorINT_MASK2[0]Not MaskedINT_LTCH2[0]
Frame out of syncINT_MASK2[5]Not MaskedINT_LTCH2[5]
Internal PLL Clock errorINT_MASK2[4]Not MaskedINT_LTCH2[4]
Digital watchdog INT_MASK2[7]Not MaskedINT_LTCH2[7]
Other Protections & StatusClass-D Over current errorINT_MASK3[3]Not MaskedINT_LTCH3[3]
Device ActiveINT_MASK0[1]MaskedINT_LTCH0[1]