The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system using serial data transmission. The address and data 8-bit bytes are transferred most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. shows a typical sequence.

To configure the TAS2563 for I²C operation set the SPII2CZ_MISO pin to ground. The I²C address can then be set using pins ADDR_SPICLK according to Table 7-3. The pin configures the two LSB bits of the following 7-bit binary address A6-A0 of 10011xx. This permits the I²C address of TAS2563 to be 0x4C(7-bit) through 0x4F(7-bit). For example, if ADDR_SPICLK is connected to ground the I²C address for the TAS2563 would be 0x4C(7-bit). This is equivalent to 0x98 (8-bit) for writing and 0x99 (8-bit) for reading. The ADDR_SPICLK should be only pulled high to the IOVDD pin voltage.

The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The device holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bi-directional bus using a wired-AND connection.

Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Pull Up Resistor can be calculated as per the table below. For Capacitive Loads different from mentioned below in table, use interpolated values.

Do not allow the SDA and SCL voltages to exceed the device supply voltage, IOVDD. The I²C pins are fault tolerant and will not load the I²C bus when the device is powered down.

Figure 7-3 Typical I²C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. Figure 7-3 shows a generic data transfer sequence.