JAJSKP5A December 2020 – September 2021 TAS2764
PRODUCTION DATA
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | *CLK_ERR_PWR_EN | RW | 0h | Clock based device power up/power down feature enable 0b = Enable clk halt detection after clock error detection 1b = Disable clock halt detection, after clock error is detected |
| 6 | *DIS_CLK_HALT | RW | 0h | Clock halt timer enable 0b = Feature disabled 1b = Feature enabled |
| 5-3 | CLK_HALT_TIMER[2:0] | RW | 3h | Clock halt timer values 0b = 820 us 1b = 3.27ms 2b = 26.21ms 3b =52.42ms 4b = 104.85ms 5b = 209.71ms 6b = 419.43ms 7b = 838.86 ms |
| 2 | IRQZ_CLR | RW | 0h | Clear INT_LATCH registers 0b = Don't clear 1b = Clear (self clearing bit) |
| 1-0 | IRQZ_PIN_CFG[1:0] | RW | 1h | IRQZ interrupt configuration. IRQZ will assert
00b = On any unmasked live interrupts 01b = On any unmasked latched interrupts 10b = For 2-4ms one time on any unmasked live interrupt event 11b = For 2-4ms every 4ms on any unmasked latched interrupts |
* Certain limitations applied. Contact TI if need to use this bit.