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TAS277020W デジタル入力、モノラル Class-D オーディオ・アンプ、スピーカー I/V 検出機能
JAJSEN9E
october 2017 – july 2023
TAS2770
PRODUCTION DATA
CONTENTS
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TAS277020W デジタル入力、モノラル Class-D オーディオ・アンプ、スピーカー I/V 検出機能
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Timing Requirements
6.7
TDM Port Timing Requirements
6.8
PDM Port Timing Requirements
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Device Mode and Address Selection
8.3.2
General I2C Operation
8.3.3
Single-Byte and Multiple-Byte Transfers
8.3.4
Single-Byte Write
8.3.5
Multiple-Byte Write and Incremental Multiple-Byte Write
8.3.6
Single-Byte Read
8.3.7
Multiple-Byte Read
8.3.8
Register Organization
8.4
Device Functional Modes
8.4.1
PDM Input
8.4.2
TDM Port
8.4.3
Playback Signal Path
8.4.3.1
High Pass Filter
8.4.3.2
Digital Volume Control and Amplifier Output Level
8.4.3.3
Audio Playback Selection
8.4.3.4
Battery Tracking Limiter with Brown Out Prevention
8.4.3.5
Inter Chip Limiter Alignment
8.4.3.5.1
TDM Mode
8.4.3.6
Class-D Settings
8.4.4
SAR ADC
8.4.5
IV Sense
8.4.6
Clocks and PLL
8.4.7
Operational Modes
8.4.7.1
Hardware Shutdown
8.4.7.2
Software Shutdown
8.4.7.3
Mute
8.4.7.4
Active
8.4.7.5
Mode Control and Software Reset
8.4.8
Faults and Status
8.4.9
Power Sequencing Requirements
8.4.10
Digital Input Pull Downs
8.5
Register Maps
8.5.1
Register Summary Table Book=0x00 Page=0x00
8.5.2
Register Maps
8.5.2.1
PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
8.5.2.2
SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
8.5.2.3
PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
8.5.2.4
PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
8.5.2.5
PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
8.5.2.6
PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
8.5.2.7
PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
8.5.2.8
MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
8.5.2.9
PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
8.5.2.10
PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
8.5.2.11
TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
8.5.2.12
TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
8.5.2.13
TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
8.5.2.14
TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
8.5.2.15
TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
8.5.2.16
TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
8.5.2.17
TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
8.5.2.18
TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
8.5.2.19
TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
8.5.2.20
TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
8.5.2.21
TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
8.5.2.22
LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
8.5.2.23
LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
8.5.2.24
LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
8.5.2.25
LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
8.5.2.26
LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
8.5.2.27
LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
8.5.2.28
BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
8.5.2.29
BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
8.5.2.30
BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
8.5.2.31
ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
8.5.2.32
ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
8.5.2.33
INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
8.5.2.34
INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
8.5.2.35
INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
8.5.2.36
INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
8.5.2.37
INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
8.5.2.38
INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
8.5.2.39
INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
8.5.2.40
VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
8.5.2.41
VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
8.5.2.42
TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
8.5.2.43
TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
8.5.2.44
INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
8.5.2.45
DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
8.5.2.46
MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
8.5.2.47
CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
8.5.2.48
TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
8.5.2.49
REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
8.5.2.50
I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
8.5.2.51
BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Overview
9.2.2.2
Select Input Capacitance
9.2.2.3
Select Decoupling Capacitors
9.2.2.4
Select Bootstrap Capacitors
9.2.3
Application Curves
9.3
Initialization Set Up
9.3.1
Initial Device Configuration - Auto Rate
9.3.2
Initial Device Configuration - 48 kHz
9.3.3
Initial Device Configuration - 44.1 kHz
9.3.4
Sample Rate Change - 48 kHz to 44.1kHz
9.3.5
Sample Rate Change - 44.1 kHz to 48 kHz
9.3.6
Device Mute
9.3.7
Device Un-Mute
9.3.8
Device Sleep
9.3.9
Device Wake
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Community Resources
12.3
Trademarks
13
Mechanical, Packaging, and Orderable Information
重要なお知らせ
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RJQ|26
MPQF497B
YFF|30
MXBG359A
サーマルパッド・メカニカル・データ
発注情報
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Data Sheet
TAS2770
20W
デジタル入力、モノラル Class-D オーディオ・アンプ、
スピーカー I/V 検出機能
このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。
1
特長
高性能モノラルClass-Dアンプ
1% THD+N で 20W (4Ω、16V)
1% THD+N で15
.4
W (4Ω、12.6V)
1W で
0.03
% THD+N (4Ω、VBAT = 12.6V)
A-Weighted アイドル・チャネル・ノイズ:32µVrms
20~20kHz において90dB PSRR、200mV
PP
リップル
1W で 82.5% の効率 (4Ω、VBAT = 12.6V)
ハードウェア・シャットダウン時の VBAT 電流:1µA 未満
42mW/63mW
のアイドル時消費電力 (8.4V/12.6V)
スピーカーの電圧および電流検出
I/V スピーカー検出によるリアルタイム診断機能
過電流
短絡(電源への短絡、グランドへの短絡、および端子間の短絡)
過熱
VBAT トラッキング・ピーク電圧リミッターとブラウンアウト防止
44.1kHz~192kHz のサンプル・レート
柔軟なユーザー・インターフェイス
I
2
S/TDM:8 チャネル (32 ビット/96kHz)
I
2
C:8 つの選択可能なアドレス
MCLK フリー動作
低いポップおよびクリック
電源
VBAT:4.5V~
16
V
AVDD:1.8V
拡散スペクトラムの低 EMI モード
過熱および過電流保護