JAJSEN9 データシート

JAJSEN9E october 2017 – july 2023 TAS2770

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RJQ|26
- MPQF497B
YFF|30
- MXBG359A

サーマルパッド・メカニカル・データ

発注情報

8.4.1 PDM Input

The TAS2770 provides one PDM input that can be used for low latency audio playback or sensor aggregation in TDM/I²C mode. Figure 8-6 below illustrates the double data rate nature of the PDM inputs. Each input has two interleaved PDM channels, one sampled by the rising edge and the other by the falling edge of the clock.

Figure 8-6 PDM Waveform

The PDM inputs are sampled by the PDMCK pin, which can be independently configured as either a PDM clock slave input or a PDM clock master output. The PDM_EDGE[1:0] and PDM_SLV[1:0] register bits select the sample clock edge and master/slave mode for each of the two PDM inputs. In master mode the PDMCK pin can disable the clocks (and drive a logic 0) by setting the PDM_GATE[1:0] register bits low. The PDM_CLK[1:0] register bits select which clock is used to sample each PDM input.

Figure 8-7 PDM Data and Clock Input Block Diagram

When configured as a clock slave, the PDM clock input does not require a specific phase relationship to the system clock (SBCLK in TDM/I²C Mode), but must have an exact frequency relationship to the audio sample rate. This is equivalent to 64/32/16 (~3 MHz) or 128/64/32 (~6 MHz) times a single/double/quadruple speed sample rate. The PDM rate is set by the PDM_RATE1[1:0] register bits.

When the PDMCK pin is configured as a clock master, the TAS2770 will output a 50% duty cycle clock of frequency that is set by the PDM_RATE1[1:0] register bits (64/32/16 or 128/64/32 times a single/double/quadruple speed sample rate).

The PDM_MAP register bit selects which PDM pin is used for audio playback input and which is used for PDM sensor input. The PDM sensor input can be decimated (time aligned with the IV sense) and transmitted on the SDOUT pin when the device is in TDM/I²C mode.

Table 8-2 PDM Input Capture Edge

PDM Input Pin	Register Bit	Value	Capture Edge
PDMD	PDM_EDGE[1]	`0`	Rising (default)
PDMD	PDM_EDGE[1]	`1`	Falling

Table 8-3 PDM Clock Slave

PDM Input Pin	Register Bit	Value	Master/Slave
PDMD	PDM_SLV[1]	`0`	Slave (default)
PDMD	PDM_SLV[1]	`1`	Master

Table 8-4 PDM Clock Select

PDM Input Pin	Register Bit	Value	Clock Source
PDMD	PDM_CLK[1]	`0`	GND
PDMD	PDM_CLK[1]	`1`	PDMCK (default)

Table 8-5 PDM Master Mode Clock Gate

PDM Clock Pin	Register Bit	Value	Gating
PDMCK	PDM_GATE[1]	`0`	Gated Off (default)
PDMCK	PDM_GATE[1]	`1`	Active

Table 8-6 PDM Input Sample Rate

PDM Input Pin	Register Bits	Value	Sample Rate
PDMD	PDM_RATE1[1:0]	`00`	2.54 - 3.38 MHz (default)
		`01`	5.08 - 6.76 MHz
		`10`	Reserved
		`11`	Reserved

Table 8-7 PDM Pin Mapping

PDM_MAP	Mapping
`0`	PDMD pin for sensor input (default)
`1`	PDMD pin for playback