JAJSEN9E october   2017  – july 2023 TAS2770

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 PDM Port Timing Requirements
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Mode and Address Selection
      2. 8.3.2 General I2C Operation
      3. 8.3.3 Single-Byte and Multiple-Byte Transfers
      4. 8.3.4 Single-Byte Write
      5. 8.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6 Single-Byte Read
      7. 8.3.7 Multiple-Byte Read
      8. 8.3.8 Register Organization
    4. 8.4 Device Functional Modes
      1. 8.4.1  PDM Input
      2. 8.4.2  TDM Port
      3. 8.4.3  Playback Signal Path
        1. 8.4.3.1 High Pass Filter
        2. 8.4.3.2 Digital Volume Control and Amplifier Output Level
        3. 8.4.3.3 Audio Playback Selection
        4. 8.4.3.4 Battery Tracking Limiter with Brown Out Prevention
        5. 8.4.3.5 Inter Chip Limiter Alignment
          1. 8.4.3.5.1 TDM Mode
        6. 8.4.3.6 Class-D Settings
      4. 8.4.4  SAR ADC
      5. 8.4.5  IV Sense
      6. 8.4.6  Clocks and PLL
      7. 8.4.7  Operational Modes
        1. 8.4.7.1 Hardware Shutdown
        2. 8.4.7.2 Software Shutdown
        3. 8.4.7.3 Mute
        4. 8.4.7.4 Active
        5. 8.4.7.5 Mode Control and Software Reset
      8. 8.4.8  Faults and Status
      9. 8.4.9  Power Sequencing Requirements
      10. 8.4.10 Digital Input Pull Downs
    5. 8.5 Register Maps
      1. 8.5.1 Register Summary Table Book=0x00 Page=0x00
      2. 8.5.2 Register Maps
        1. 8.5.2.1  PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
        2. 8.5.2.2  SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
        3. 8.5.2.3  PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
        4. 8.5.2.4  PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
        5. 8.5.2.5  PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
        6. 8.5.2.6  PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
        7. 8.5.2.7  PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
        8. 8.5.2.8  MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
        9. 8.5.2.9  PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
        10. 8.5.2.10 PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
        11. 8.5.2.11 TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
        12. 8.5.2.12 TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
        13. 8.5.2.13 TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
        14. 8.5.2.14 TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
        15. 8.5.2.15 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
        16. 8.5.2.16 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
        17. 8.5.2.17 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
        18. 8.5.2.18 TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
        19. 8.5.2.19 TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
        20. 8.5.2.20 TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
        21. 8.5.2.21 TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
        22. 8.5.2.22 LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
        23. 8.5.2.23 LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
        24. 8.5.2.24 LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
        25. 8.5.2.25 LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
        26. 8.5.2.26 LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
        27. 8.5.2.27 LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
        28. 8.5.2.28 BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
        29. 8.5.2.29 BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
        30. 8.5.2.30 BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
        31. 8.5.2.31 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
        32. 8.5.2.32 ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
        33. 8.5.2.33 INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
        34. 8.5.2.34 INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
        35. 8.5.2.35 INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
        36. 8.5.2.36 INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
        37. 8.5.2.37 INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
        38. 8.5.2.38 INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
        39. 8.5.2.39 INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
        40. 8.5.2.40 VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
        41. 8.5.2.41 VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
        42. 8.5.2.42 TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
        43. 8.5.2.43 TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
        44. 8.5.2.44 INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
        45. 8.5.2.45 DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
        46. 8.5.2.46 MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
        47. 8.5.2.47 CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
        48. 8.5.2.48 TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
        49. 8.5.2.49 REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
        50. 8.5.2.50 I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
        51. 8.5.2.51 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Overview
        2. 9.2.2.2 Select Input Capacitance
        3. 9.2.2.3 Select Decoupling Capacitors
        4. 9.2.2.4 Select Bootstrap Capacitors
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Initial Device Configuration - Auto Rate
      2. 9.3.2 Initial Device Configuration - 48 kHz
      3. 9.3.3 Initial Device Configuration - 44.1 kHz
      4. 9.3.4 Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5 Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6 Device Mute
      7. 9.3.7 Device Un-Mute
      8. 9.3.8 Device Sleep
      9. 9.3.9 Device Wake
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.2 TDM Port

The TAS2770 provides a flexible TDM serial audio port for use in TDM/I2C Mode. The port can be configured to support a variety of formats including stereo I2S, Left Justified and TDM. Mono audio playback is available via the SDIN pin. The SDOUT pin is used to transmit sample streams including speaker voltage and current sense, VBAT voltage, die temperature and channel gain.

The TDM serial audio port supports up to 8 32-bit time slots at 44.1/48 kHz, 4 32-bit time slots at a 88.2/96 kHz sample rate and 2 32-bit time slots at a 176.4/192 kHz sample rate. The device supports 2 time slots at 32 bits in width and 4 or 8 time slots at 16, 24 or 32 bits in width. Valid SBCLK to FSYNC ratios are 64, 96, 128, 192, and 256.. Note that the device will automatically detect the number of time slots and this does not need to be programmed.

By default, the TAS2770 will automatically detect the PCM playback sample rate. This can be disabled by setting the AUTO_RATE register bit high.

The SAMP_RATE[2:0] register bits set the PCM audio sample rate when AUTO_RATE = 1. The TAS2770 employs a robust clock fault detection engine that will automatically volume ramp down the playback path if FSYNC does not match the configured sample rate (if AUTO_RATE = 1) or the ratio of SBCLK to FSYNC is not supported (minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and ratio, the device will automatically volume ramp the playback path back to the configured volume and resume playback.

Table 8-8 PCM Auto Sample Rate Detection
AUTO_RATESetting
0
Enabled (default)
1
Disabled
Table 8-9 PCM Audio Sample Rates
SAMP_RATE[1:0]Sample Rate
000
Reserved
001
Reserved
010
Reserved
011
44.1 kHz / 48 kHz (default)
100
88.2 kHz / 96 kHz
101
176.4 kHz / 192 kHz
110
Reserved
111
Reserved

Figure 8-8 and Figure 8-9 below illustrates the receiver frame parameters required to configure the port for playback. A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge (set by the RX_EDGE register bit). The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from the transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format and 1 for an I2S format.

GUID-A54E39C8-D547-44B1-9564-B3F913E3A508-low.gifFigure 8-8 TDM RX Time Slot with Left Justification
GUID-4642966B-F4AB-4D24-AE78-C84D8A56AE17-low.gifFigure 8-9 TDM RX Time Slots
Table 8-10 TDM Start of Frame Polarity
FRAME_STARTPolarity
0
Low to High on FSYNC
1
High to Low on FSYNC (default)
Table 8-11 TDM RX Capture Polarity
RX_EDGEFSYNC and SDIN Capture Edge
0
Rising edge of SBCLK (default)
1
Falling edge of SBCLK
Table 8-12 TDM RX Start of Frame to Time Slot 0 Offset
RX_OFFSET[4:0]SBCLK Cycles
0x00
0
0x01
1 (default)
0x02
2
...
...
0x1E
30
0x1F
31

The RX_SLEN[1:0] register bits set the length of the RX time slot. The length of the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will left justify the audio sample within the time slot by default, but this can be changed to right justification via the RX_JUSTIFY register bit. The TAS2770 supports mono and stereo down mix playback ([L+R]/2) via the left time slot, right time slot and time slot configuration register bits (RX_SLOT_L[3:0], RX_SLOT_R[3:0] and RX_SCFG[1:0] respectively). By default the device will playback mono from the time slot equal to the I2C base address offset (set by the MODE pin) for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot, right time slot or stereo down mix set by the RX_SLOT_L[3:0] and RX_SLOT_R[3:0] register bits.

If time slot selections places reception either partially or fully beyond the frame boundary, the receiver will return a null sample equivalent to a digitally muted sample.

Table 8-13 TDM RX Time Slot Length
RX_SLEN[1:0]Time Slot Length
00
16-bits
01
24-bits
10
32-bits (default)
11
reserved
Table 8-14 TDM RX Sample Word Length
RX_WLEN[1:0]Length
00
16-bits
01
20-bits
10
24-bits (default)
11
32-bits
Table 8-15 TDM RX Sample Justification
RX_JUSTIFYJustification
0
Left (default)
1
Right
Table 8-16 TDM RX Time Slot Select Configuration
RX_SCFG[1:0]Config Origin
00
Mono with Time Slot equal to I2C Address Offset (default)
01
Mono Left Channel
10
Mono Right Channel
10
Stereo Down Mix [L+R]/2
Table 8-17 TDM RX Left Channel Time Slot
RX_SLOT_L[3:0]Time Slot
0x0
0 (default)
0x1
1
...
...
0xE
14
0xF
15
Table 8-18 TDM RX Right Channel Time Slot
RX_SLOT_R[3:0]Time Slot
0x0
0 (default)
0x1
1
...
...
0xE
14
0xF
15

The TDM port can transmit a number sample streams on the SDOUT pin including speaker voltage sense, speaker current sense, decimated PDM input, VBAT voltage, die temperature and channel gain. Figure 8-10 below illustrates the alignment of time slots to the beginning of a frame and how a given sample stream is mapped to time slots. Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin, which can be configured by setting the TX_EDGE register bit. The TX_OFFSET[2:0] register bits define the number SBCLK cycles between the start of a frame and the beginning of time slot 0. This would typically be programmed to 0 for Left Justified format and 1 for I2S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the setting of the TX_FILL register bit setting. An optional bus keeper will weakly hold the state of SDOUT when all devices driving are Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the TX_KEEPER register bit.

Each sample stream is composed of either one or two 8-bit time slots. Speaker voltage sense, speaker current sense and decimated PDM sample streams are 16-bit precision, so they will always utilize two TX time slots. The VBAT voltage stream is 12-bit precision, and can either be transmitted left justified in a 16-bit word (using two time slots) or can be truncated to 8-bits (the top 8 MSBs) and be transmitted in a single time slot. This is configured by setting VBAT_SLEN register bit. The Die temperature and gain are both 8-bit precision and are transmitted in a single time slot.

GUID-70466F93-6341-4AEA-BF1F-CAAC2A713A98-low.gif Figure 8-10 TDM Port TX Diagram
Table 8-19 TDM TX Transmit Polarity
TX_EDGESDOUT Transmit Edge
0
Rising edge of SBCLK
1
Falling edge of SBCLK (default)
Table 8-20 TDM TX Start of Frame to Time Slot 0 Offset
TX_OFFSET[2:0]SBCLK Cycles
0x0
0
0x1
1 (default)
0x2
2
...
...
0x6
6
0x7
7
Table 8-21 TDM TX Unused Bit Field Fill
TX_FILLSDOUT Unused Bit Fields
0
Transmit 0
1
Transmit Hi-Z (default)
Table 8-22 TDM TX SDOUT Bus Keeper Enable
TX_KEEPERSDOUT Bus Keeper
0
Disable bus keeper
1
Enable bus keeper (default)

The time slot register for each sample stream defines where the MSB transmission begins. For instance, if VSNS_SLOT[5:0] is set to 2, the upper 8 MSBs will be transmitted in time slot 2 and the lower 8 LSBs will be transmitted in time slot 3. Each sample stream can be individually enabled or disabled. This is useful to manage limited TDM bandwidth since it may not be necessary to transmit all streams for all devices on the bus.

It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. For instance, if VSNS_SLOT[5:0] is set to 2 and ISNS_SLOT[5:0] is set to 3, the lower 8 LSBs of voltage sense will conflict with the upper 8 MSBs of current sense. This will produce unpredictable transmission results in the conflicting bit slots (i.e. the priority is not defined).

If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at the frame boundary.

Table 8-23 TDM Voltage Sense Time Slot
VSNS_SLOT[5:0]Slot
0x00
0 (default)
0x01
1
0x02
2
...
...
0x3E
62
0x3F
63
Table 8-24 TDM Voltage Sense Transmit Enable
VSNS_TXState
0
Disabled (default)
1
Enabled
Table 8-25 TDM Current Sense Time Slot
ISNS_SLOT[5:0]Slot
0x00
0
0x01
1
0x02
2 (default)
...
...
0x3E
62
0x3F
63
Table 8-26 TDM Current Sense Transmit Enable
ISNS_TXState
0
Disabled (default)
1
Enabled
Table 8-27 TDM Decimated PDM Input Time Slot
PDM_SLOT[5:0]Slot
0x00
0
0x01
1
...
...
0x04
4 (default)
...
...
0x3E
62
0x3F
63
Table 8-28 TDM Decimated PDM Input Transmit Enable
PDM_TXState
0
Disabled (default)
1
Enabled
Table 8-29 TDM VBAT Time Slot
VBAT_SLOT[5:0]Slot
0x00
0
0x01
1
...
...
0x06
6 (default)
...
...
0x3E
62
0x3F
63
Table 8-30 TDM VBAT Time Slot Length
VBAT_SLENSlot Length
0
Truncate to 8-bits (default)
1
Left justify to 16-bits
Table 8-31 TDM VBAT Transmit Enable
VBAT_TXState
0
Disabled (default)
1
Enabled
Table 8-32 TDM Temp Sensor Time Slot
TEMP_SLOT[5:0]Slot
0x00
0
0x01
1
...
...
0x07
7 (default)
...
...
0x3E
62
0x3F
63
Table 8-33 TDM Temp Sensor Transmit Enable
TEMP_TXState
0
Disabled (default)
1
Enabled
Table 8-34 TDM Limiter Gain Reduction Time Slot
GAIN_SLOT[5:0]Slot
0x00
0
0x01
1
...
...
0x08
8 (default)
...
...
0x3E
62
0x3F
63
Table 8-35 TDM Limiter Gain Reduction Transmit Enable
GAIN_TXState
0
Disabled (default)
1
Enabled