JAJSFI3A May 2018 – November 2018 TAS3251
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | PLCK | Reserved | PLLE | ||||
R/W | R | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | Reserved | R/W | Reserved | |
4 | PLCK | R | 0 | PLL Lock Flag – This bit indicates whether the PLL is locked or not. When the PLL is disabled this bit always shows that the PLL is not locked.
0: The PLL is locked
|
3-1 | Reserved | R/W | Reserved | |
0 | PLLE | R/W | 1 | PLL Enable – This bit enables or disables the internal PLL. When PLL is disabled, the master clock will be switched to the MCLK.
0: Disable PLL
|